Transmeta CrusoeBackground -- ChipsetsNorthBridge / SouthBridgeIntel Hub ArchitectureOutlineTransmeta Innovation TimelineCrusoe Processor FamilySlide 8Characteristics of CrusoeCharacteristics of Crusoe contd.ArchitectureCrusoe Processorx86 CPU vs. CrusoeCrusoe Hardware/Software PartitioningProcessor DetailsProcessor Block DiagramSlide 17Architecture DetailsCrusoe Processor HierarchyCrusoe: A Native VLIW ProcessorInstruction Word - VLIWCode Morphing SoftwareEfficeon TM8800 ProcessorInstruction SetRegistersRegisters contd.Instruction EncodingInstruction Encoding Continued….Format of ALUsFormat of ALUs Continued….Format of Load/Store UnitFormat of Load/Store Unit Continued….Slide 33Slide 34PipeliningSlide 36Pipeline StagesDecoding and SchedulingSlide 39Decoding and Scheduling Continued….Code MorphingCode Morphing System (CMS)Slide 43Slide 44Code Morphing BenefitsCode Morphing Benefits contd..Dynamic Translation using ChainingPerforming a TranslationTranslation ExampleTranslation Step 1Translation Step 2Translation Step 3CMS Translation CacheCode OptimizationSlide 55Hardware Support for Code MorphingShadow RegistersGated Store BuffersExceptionsException HandlingAlias Hardware for Data SpeculationMoving Loads Ahead of StoresMemory-mapped I/OHandling Self-Modifying CodeOther Remarks about Code MorphingCrusoe Performance DisadvantagesCrusoe Performance DisadvantagesPower ManagementLongRun Dynamic Power ManagementLongRun OverviewPower Management StatesSlide 72Power Management State DiagramLongRun Power ManagementLongRun Power AdjustmentsSlide 76Typical Operating Power per StatePower ComparisonLongRun Thermal ManagementMemorySlide 81DDR Memory InterfaceSlide 83Slide 84DDR Memory Interface ConstraintsDDR Memory Rank and Chip Select ExamplesSlide 87SDR Memory InterfaceSlide 89Slide 90Clocks And TimingClocksSlide 93Slide 94Slide 95Slide 96Slide 97Slide 98Slide 99Slide 100Slide 101Slide 102Processor Pin LayoutSlide 104Target Applications and Sample CodeTarget ApplicationsSlide 107Slide 108Slide 109Slide 110Slide 111ReferencesCS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 1CS433Processor Presentation SeriesProf. Luddy HarrisonTransmeta CrusoeCS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 2Background -- ChipsetsNorthBrigdgeGraphics and Memory Controller HubOriginally, this contained the PCI controllerSouthBridgeI/O Controller HubIntel Hub ArchitectureThis is a later version of the same functionalityCS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 3NorthBridge / SouthBridgeCS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 4Intel Hub ArchitectureCS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 5OutlineTransmeta Innovation TimelineCrusoe Processor Family and OverviewArchitecture showing Data paths, Registers, ALU, etc.Instruction SetPipeliningCode MorphingLongRun Power ManagementMemory Map and Support for Internal and External MemoriesClocks and TimingProcessor Pin LayoutTarget Applications, Specific Use, and Sample Assembly Language Code for application kernelsCS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 6Transmeta Innovation TimelineDave Ditezel, of RISC-fame and formerly from SPARC, started up Transmeta as its CEO in 1995.The first Patent (5958061) was applied in July 24, 1996 granted in September 28, 1999.On January 19, 2000 the Crusoe processor was published. Crusoe became famous as an x86 compatible family of solutions that combines strong performance with remarkably low power consumption.CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 7Crusoe Processor FamilyTM5400 -- 500-700MHz, 256K L2 Cache TM5500 -- 0.13µ, 667-800MHz, 256K L2 Cache TM5600 -- 500-700MHz, 512K L2 Cache TM5800 -- 0.13µ, 667-800MHz, 512K L2 Cache SE TM55E/TM58E -- 0.13µ, 800MHz, 256K L2 cacheEmbedded version of Crusoe processorPresentation focuses on TM5800 as the representative processor in this familyCS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 8 Crusoe ProcessorModel TM5500Crusoe ProcessorModel TM5800Crusoe SE ProcessorModel TM55ECrusoe SE ProcessorModel TM58E667 MHz 800 MHz - 1 GHz 800 MHz - 1 GHz 800 MHz - 1 GHz128 KByte L1 Cache (64KByte L1 cache128 KByte L1 Cache (64KByte L1 cache128 KByte L1 Cache (64KByte L1 cache128 KByte L1 Cache (64KByte L1 cache256KB L2 write-back cache 256KB L2 write-back cache 256KB L2 write-back cache 256KB L2 write-back cacheIntegrated Northbridge64-bit, 133 MHz DDR memory controller64-bit, 133 MHz SDR memory controller32-bit, 33 MHz, 3.3V PCI busIntegrated Northbridge64-bit, 133 MHz DDR memory controller64-bit, 133 MHz SDR memory controller32-bit, 33 MHz, 3.3V PCI busIntegrated Northbridge64-bit, 133 MHz DDR memory controller64-bit, 133 MHz SDR memory controller32-bit, 33 MHz, 3.3V PCI busIntegrated Northbridge64-bit, 133 MHz DDR memory controller64-bit, 133 MHz SDR memory controller32-bit, 33 MHz, 3.3V PCI busMMX Instruction Support MMX Instruction Support MMX Instruction Support MMX Instruction Support0.13µm process 0.13µm process 0.13µm process 0.13µm processCompact 474-pin Ceramic BGA PackageCompact 474-pin Ceramic BGA PackageCompact 474-pin Ceramic BGA PackageCompact 474-pin Ceramic BGA PackageMax TDP: 5.1W Max TDP: 5.1W Max TDP: 5.1W Max TDP: 5.1WSupports T-junction temperatures of 100CSupports T-junction temperatures of 100CRated for 24/7 operation for 10 yearsRated for 24/7 operation for 10 yearsCS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 9Characteristics of Crusoe4 Instruction Issue, 128-Bit VLIW EngineFully Pentium 4-ISA compatibleUp to four instructions issued per clock cycleMMX multimedia extensions512 MB L2 cacheAdvanced Code Morphing Software (CMS)Unique software-based architecture is key to reducing power consumption and enabling future scalability and flexibilityIntegrated Northbridge Core LogicOn-chip SDR and DDR-266 memory interfacesOn-chip 32-bit, 33 MHz PCI bus controllerCS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 10Characteristics of Crusoe contd.LongRun Dynamic Power ManagementEnables low power operation by dynamically adjusting operating frequency and voltage to match the performance requirements of application workloads.Provides higher performance within smaller, thermally constrained environmentsEnables fanless designs for quieter and more