CS433: Computer System OrganizationHistory8086 / 8088 (1978)Intel 286 (1982)Intel 386 (1985)Intel 486 (1989)Intel Pentium (1993)Intel P6 (1995 – 1999)Pentium ProPentium IIPentium II XeonCeleronPentium IIIPentium III XeonPentium 4 (2000)Pentium 4 Supporting Hyper-Threading Technology (2004)Intel Xeon (2001-2004)Intel Pentium M (2003)Slide 19Slide 20Slide 21NetBurst MicroArchitecture (Pentium 4)Slide 23Front-End PipelineSlide 25Instruction LayoutIA32 Instruction FormatSlide 28RegistersSlide 30Slide 31Special Register PurposesOverlaid RegistersEFLAGSSystem Status in EFLAGSData TypesFundamental Data TypesSlide 38Floating Point TypesSlide 40IEEE 754 and IA32Example of Semantic Difference Between Natural x86 Execution and C SemanticsOperating on NaNsPointer TypesDisadvantages of Far Pointers?SIMDMMX Types (64-bits)Slide 48BCD (Binary Coded Decimal)MemorySlide 51Memory ModelsSlide 53Segment SelectorsSeg Regs in Flat Mem ModelSegmented Memory ModelConstructing an AddressDefault SegmentsOffset CalculationSlide 60Flat ModelSystem Table RegistersProtected Flat ModelMulti-Segment Model01/14/19 CS433 Luddy Harrison 1CS433: Computer System OrganizationLuddy HarrisonIntel IA32 Architecture01/14/19 CS433 Luddy Harrison 2HistoryThe x86 / IA32 family01/14/19 CS433 Luddy Harrison 38086 / 8088 (1978)16-bit registers16-bit external data bus (8086)8-bit external data bus (8088)20-bit address space via segment registers01/14/19 CS433 Luddy Harrison 4Intel 286 (1982)segment registers point to descriptor tablesdescriptors have 24-bit segment addressessegment swappingprotectionbounds checking on segmentsread/execute/write checkingfour privelege levels01/14/19 CS433 Luddy Harrison 5Intel 386 (1985)32-bit registers (data and address)virtual 8086 mode32-bit address bussegmented memory model + flat memory modelpaging with 4Kbyte pagespipelined execution (decode + execution)01/14/19 CS433 Luddy Harrison 6Intel 486 (1989)five stage pipeline8Kb on-chip L1 cachewrite-throughintegrated x87 FPUpower management01/14/19 CS433 Luddy Harrison 7Intel Pentium (1993)two pipelines, u and vsuperscalar execution8kb data + 8kb instruction on-chip L1 cacheswrite-back option in addition to write-throughbranch predictionburstable 64-bit external data busmultiprocessor support[second stepping: MMX]01/14/19 CS433 Luddy Harrison 8Intel P6 (1995 – 1999)Pentium ProPentium IIPentium II XeonCeleronPentium IIIPentium III Xeon01/14/19 CS433 Luddy Harrison 9Pentium Pro3-way superscalarout-of-ordermore aggressive branch predictionspeculative executionL1 + L2 cache on chip8K + 8K L1256K L201/14/19 CS433 Luddy Harrison 10Pentium IIMMX (in P6 family)16K + 16K L1 caches256K, 512K, 1M L2 caches supportedimproved power management01/14/19 CS433 Luddy Harrison 11Pentium II Xeonimproved multiprocessor support4- and 8-way systems2Mb L2 cache on chip01/14/19 CS433 Luddy Harrison 12Celeronlow-priced / reduced power market128K L2 cachecheaper package (plastic)01/14/19 CS433 Luddy Harrison 13Pentium IIIStreaming SIMD Extensions (SSE)128-bit registersfloating point vector types01/14/19 CS433 Luddy Harrison 14Pentium III Xeonimproved cache01/14/19 CS433 Luddy Harrison 15Pentium 4 (2000)return to Arabic numeralsNetBurst microarchitectureSSE2 and SSE301/14/19 CS433 Luddy Harrison 16Pentium 4 Supporting Hyper-Threading Technology (2004)marketing team abandons names in favor of entire sentencesHyper-Threading is Simultaneous MultiThreading01/14/19 CS433 Luddy Harrison 17Intel Xeon (2001-2004)internal revolt against long namerecycled portion of old name(s) prevailsmultiprocessor supportWas this the first Hyper-Threading IA32?01/14/19 CS433 Luddy Harrison 18Intel Pentium M (2003)The M is not a Roman Numeralnot “Pentium 1000”refers to “Mobile”low-powerintegrated wireless support01/14/19 CS433 Luddy Harrison 1901/14/19 CS433 Luddy Harrison 2001/14/19 CS433 Luddy Harrison 2101/14/19 CS433 Luddy Harrison 22NetBurst MicroArchitecture (Pentium 4)deep branch predictiondynamic dataflow analysisinstructions translated into a risc-like formthese in turn are subject to out-of-order executionspeculative executionup to 126 instructions in flightup to 48 loads and 24 stores in pipelineadvanced branch predictor4K branch target bufferexecution trace cache stores decoded instructionsstraightens code on the fly!8-way L2 cache64-byte cache line sizeexternal bus capable of 6.4Gbytes per second01/14/19 CS433 Luddy Harrison 2301/14/19 CS433 Luddy Harrison 24Front-End PipelinePrefetchFetch (on prefetch fail)Decode into micro-operationsGenerate microcode from complex operationsDelivers decoded instructions from execution trace cacheBranch prediction01/14/19 CS433 Luddy Harrison 2501/14/19 CS433 Luddy Harrison 26Instruction LayoutSee The Intel Manuals for Details01/14/19 CS433 Luddy Harrison 27IA32 Instruction Format01/14/19 CS433 Luddy Harrison 28What can you say about writing an optimizing compiler for IA32?01/14/19 CS433 Luddy Harrison 29Registers01/14/19 CS433 Luddy Harrison 30User-Visible Architectural State01/14/19 CS433 Luddy Harrison 3101/14/19 CS433 Luddy Harrison 32Special Register Purposes01/14/19 CS433 Luddy Harrison 33Overlaid Registers01/14/19 CS433 Luddy Harrison 34EFLAGS01/14/19 CS433 Luddy Harrison 35System Status in EFLAGS01/14/19 CS433 Luddy Harrison 36Data Types01/14/19 CS433 Luddy Harrison 37Fundamental Data Types01/14/19 CS433 Luddy Harrison 3801/14/19 CS433 Luddy Harrison 39Floating Point Types01/14/19 CS433 Luddy Harrison 4001/14/19 CS433 Luddy Harrison 41IEEE 754 and IA32Kahan et al formulated the proper working of floating point hardware in a documented standard known as IEEE 754The x86 was designed to do all “scratch” calculations using a small floating point stackthe entries on the stack are 80-bit extended precision numbersUnfortunately, this does not correspond well to the semantics of C01/14/19 CS433 Luddy Harrison 42Example of Semantic Difference Between Natural x86 Execution and C Semanticsdouble A, B, C, D, E, F, G;// set B=D=F and C=E=G and let B*C be very close to 0 in// extended precision, but exactly 0 in double precision....// suppose we use the x86 FP stack to do this RHS:A = B*C + D*E - F*G; // this yields