ELEC 5970-001/6970-001(Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits Pseudo-nMOS, Dynamic CMOS and Domino CMOS LogicWhy Not Static CMOS?A Pseudo-nMOS GateA Pseudo-nMOS InverterPerformance of Pseudo-nMOSNegative Aspects of Pseudo-nMOSA Dynamic CMOS GateTwo-Phase Operation in a Vector Period4-Input NAND Dynamic CMOS GateCharacteristics of Dynamic CMOSLogic ActivityCharge LeakageBleeder TransistorA Problems With Dynamic CMOSDomino CMOSBleeder in Domino CMOSLogic Mapping for Noninverting GatesSelecting a Logic Style10/25/05 ELEC 5970-001/6970-001 Lecture 15 1ELEC 5970-001/6970-001(Fall 2005)Special Topics in Electrical EngineeringLow-Power Design of Electronic CircuitsPseudo-nMOS, Dynamic CMOSand Domino CMOS LogicVishwani D. AgrawalJames J. Danaher ProfessorDepartment of Electrical and Computer EngineeringAuburn Universityhttp://www.eng.auburn.edu/[email protected]/25/05 ELEC 5970-001/6970-001 Lecture 15 2Why Not Static CMOS?•Advantages: Static (robust) operation, low power, scalable with technology.•Disadvantages:–Large size: An N input gate requires 2N transistors.–Large capacitance: Each fanout must drive two devices.•Alternatives: Pass-transistor logic (PTL), pseudo-nMOS, dynamic CMOS, domino CMOS.10/25/05 ELEC 5970-001/6970-001 Lecture 15 3A Pseudo-nMOS GatePUNPDNVDDCMOS GatePDNVDDPseudo-nMOS GateOutputInputsInputsOutput10/25/05 ELEC 5970-001/6970-001 Lecture 15 4A Pseudo-nMOS InverterW/Lp = 4W/Lp = 2W/Lp = 0.25W/Lp= 0.5W/Lp= 10.0 0.5 1.0 1.5 2.0 2.5Input voltage, VOutput voltage, V3.02.52.01.51.00.50.0Nominal device: W 0.5μ── = ──── = 2 Ln0.25μ10/25/05 ELEC 5970-001/6970-001 Lecture 15 5Performance of Pseudo-nMOSSize, W/LpLogic 0 voltageLogic 0 static powerDelay0 → 14 0.693 V 564 μW 14 ps2 0.273 V 298 μW 56 ps1 0.133 V 160 μW 123 ps0.5 0.064 V 80 μW 268 ps0.25 0.031 V 41 μW 569 psJ. M. Rabaey, A. Chandrakasan and B. Nokolić, Digital IntegratedCircuits, Upper Saddle River, New Jersey: Pearson Education, 2003.10/25/05 ELEC 5970-001/6970-001 Lecture 15 6Negative Aspects of Pseudo-nMOS•Output 0 state is ratioed logic.•Faster gates mean higher static power.•Low static power means slow gates.10/25/05 ELEC 5970-001/6970-001 Lecture 15 7A Dynamic CMOS GatePDNVDDInputsOutputCKCL10/25/05 ELEC 5970-001/6970-001 Lecture 15 8Two-Phase Operation in a Vector PeriodPhase CK Inputs OutputPrecharge low don’t care highEvaluation high Valid inputs Valid outputs10/25/05 ELEC 5970-001/6970-001 Lecture 15 94-Input NAND Dynamic CMOS GateOutput= CK’ + (ABCD)’∙ CKCLCKABCDCKVDD tL→H ≈ 010/25/05 ELEC 5970-001/6970-001 Lecture 15 10Characteristics of Dynamic CMOS•Nonratioed logic – sizing of pMOS transistor is not important for output levels.•Larger precharge transistor reduces output fall time, but increases precharge power. Faster switching due to smaller capacitance.•Static power – negligible.•Short-circuit power – none.•Dynamic power–no glitches – following precharge, signals can either make transitions only in one direction, 1→0, or no transition, 1→1.–only logic transitions – all nodes at logic 0 are charged to VDD during precharge phase.10/25/05 ELEC 5970-001/6970-001 Lecture 15 11Logic Activity•Probability of 0 → 1 transition:–Static CMOS, p0 p1 = p0(1 – p0)–Dynamic CMOS, p0•Example: 2-input NOR gate–Static CMOS, Pdyn = 0.1875 CLVDD2fCK–Dynamic CMOS, Pdyn = 0.75 CLVDD2fCK p1=0.5 p1=0.5 p1=0.25 p0=0.7510/25/05 ELEC 5970-001/6970-001 Lecture 15 12Charge LeakageOutputA’CLCKA=0CKVDDCKA’TimePrechargeEvaluateIdealActualJ. M. Rabaey, A. Chandrakasan and B. Nokolić, Digital IntegratedCircuits, Upper Saddle River, New Jersey: Pearson Education, 2003.10/25/05 ELEC 5970-001/6970-001 Lecture 15 13Bleeder TransistorOutputCLCKABCDCKVDDOutputCLCKABCDCKVDD10/25/05 ELEC 5970-001/6970-001 Lecture 15 14A Problems With Dynamic CMOSCKA=0→1CKVDDCKABCBJ. M. Rabaey, A. Chandrakasan and B. Nokolić, Digital IntegratedCircuits, Upper Saddle River, New Jersey: Pearson Education, 2003.CKCKVDDC prech. evaluate10/25/05 ELEC 5970-001/6970-001 Lecture 15 15Domino CMOSCKA=0→1CKVDDCKABCBR. H. Krambeck, C. M. Lee and H.-F. S. Law, “High-Speed Compact Circuits with CMOS,” IEEE J. Solid-State Circuits, vol. SC-17, no. 3, pp. 614-619, June 1982.CKCKVDDC prech. evaluate10/25/05 ELEC 5970-001/6970-001 Lecture 15 16Bleeder in Domino CMOSOutputCLCKABCDCKVDD10/25/05 ELEC 5970-001/6970-001 Lecture 15 17Logic Mapping for Noninverting GatesABCDEFGHABCG+HANDORAND/ORXYYABCDEFG+H10/25/05 ELEC 5970-001/6970-001 Lecture 15 18Selecting a Logic Style•Static CMOS: most reliable and predictable, reasonable in power and speed, voltage scaling and device sizing are well understood.•Pass-transistor logic: beneficial for multiplexer and XOR dominated circuits like adders, etc.•For large fanin gates, static CMOS is inefficient; a choice can be made between pseudo-nMOS, dynamic CMOS and domino