ELEC 5970-001/6970-001(Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits Dynamic Power: Glitch EliminationComponents of PowerPower of a TransitionDynamic PowerGlitch Power ReductionTheorem 1Event PropagationInertial Delay of a GateTheorem 2Minimum Transient DesignBalanced Delay MethodHazard Filter MethodLinear ProgramVariables for Full Adder add1bSlide 15Objective FunctionSpecify Critical Path DelayMulti-Input Gate ConditionResults: 1-Bit AdderAMPL Solution: maxdel = 6AMPL Solution: maxdel = 7AMPL Solution: maxdel ≥ 11Original 1-Bit AdderOptimized 1-Bit AdderSlide 25ReferencesA LimitationTiming WindowSlide 29Multiple-Input Gate ConstraintsSingle-Input Gate ConstraintsOverall Delay ConstraintsComparison of ConstraintsEstimation of PowerResults: 4-Bit ALUPower Calculation in SpicePower Dissipation of ALU4F0 Output of ALU4Benchmark CircuitsPhysical DesignSlide 41Slide 42Conclusion9/20/05 ELEC 5970-001/6970-001 Lecture 8 1ELEC 5970-001/6970-001(Fall 2005)Special Topics in Electrical EngineeringLow-Power Design of Electronic CircuitsDynamic Power: Glitch EliminationVishwani D. AgrawalJames J. Danaher ProfessorDepartment of Electrical and Computer EngineeringAuburn Universityhttp://www.eng.auburn.edu/[email protected]/20/05 ELEC 5970-001/6970-001 Lecture 8 2Components of Power•Dynamic–Signal transitions•Logic activity•Glitches–Short-circuit•Static–Leakage9/20/05 ELEC 5970-001/6970-001 Lecture 8 3Power of a TransitionVVDDDDGroundGroundCLRRDynamic Power= CLVDD2/2 + PscViVoisc9/20/05 ELEC 5970-001/6970-001 Lecture 8 4Dynamic Power•Each transition of a gate consumes CV2/2.•Methods of power saving:–Minimize load capacitances•Transistor sizing•Library-based gate selection–Reduce transitions•Logic design•Glitch reduction9/20/05 ELEC 5970-001/6970-001 Lecture 8 5Glitch Power Reduction•Design a digital circuit for minimum transient energy consumption by eliminating hazards9/20/05 ELEC 5970-001/6970-001 Lecture 8 6Theorem 1•For correct operation with minimum energy consumption, a Boolean gate must produce no more than one event per transition.Output logic state changesOne transition is necessaryOutput logic state unchangedNo transition is necessary9/20/05 ELEC 5970-001/6970-001 Lecture 8 7Event Propagation2 4 611 353100022Path P1P2Path P3Single lumped inertial delay modeled for each gatePI transitions assumed to occur without time skew9/20/05 ELEC 5970-001/6970-001 Lecture 8 8Inertial Delay of a GatedHLdLH dHL+dLH d = ──── 2VinVouttime9/20/05 ELEC 5970-001/6970-001 Lecture 8 9•Given that events occur at the input of a gate with inertial delay d at times,t1 ≤ . . . ≤ tn , the number of events at the gate output cannot exceedTheorem 2min ( min ( n n , 1 + ), 1 + )ttnn – t – t11----------------dd ttnn - t - t11 tt11 t t22 t t33 t tnn timetime9/20/05 ELEC 5970-001/6970-001 Lecture 8 10Minimum Transient Design•Minimum transient energy condition for a Boolean gate:| t| tii - t - tjj | < d | < d Where tWhere tii and t and tjj are arrival times of input are arrival times of inputevents and d is the inertial delay of gateevents and d is the inertial delay of gate9/20/05 ELEC 5970-001/6970-001 Lecture 8 11Balanced Delay Method•All input events arrive simultaneously•Overall circuit delay not increased•Delay buffers may have to be inserted11111111111111113311114?4?9/20/05 ELEC 5970-001/6970-001 Lecture 8 12Hazard Filter Method•Gate delay is made greater than maximum input path delay difference•No delay buffers needed (least transient energy)•Overall circuit delay may increase331111111133111111119/20/05 ELEC 5970-001/6970-001 Lecture 8 13Linear Program•Variables: gate and buffer delays•Objective: minimize number of buffers•Subject to: overall circuit delay•Subject to: minimum transient condition for multi-input gate9/20/05 ELEC 5970-001/6970-001 Lecture 8 14Variables for Full Adder add1b111111111111111111000000000000000000000000009/20/05 ELEC 5970-001/6970-001 Lecture 8 15Variables for Full Adder add1b•Gate delay variables d4 . . . d12•Buffer delay variables d15 . . . d299/20/05 ELEC 5970-001/6970-001 Lecture 8 16Objective Function•Ideal: minimize the number of non-zero delay buffers•Actual: sum of buffer delays9/20/05 ELEC 5970-001/6970-001 Lecture 8 17Specify Critical Path Delay11111111111111111100000000000000000000000000Sum of delays on critical path ≤ Sum of delays on critical path ≤ maxdelmaxdel9/20/05 ELEC 5970-001/6970-001 Lecture 8 18Multi-Input Gate Condition11111111000000000000d1d1d2d2ddd1 - d2 ≤ dd1 - d2 ≤ dd2 - d1 ≤ dd2 - d1 ≤ ddddd|d1 - d2| ≤ d ≡|d1 - d2| ≤ d ≡9/20/05 ELEC 5970-001/6970-001 Lecture 8 19Results: 1-Bit Adder9/20/05 ELEC 5970-001/6970-001 Lecture 8 20AMPL Solution: maxdel = 622111111111122112222119/20/05 ELEC 5970-001/6970-001 Lecture 8 21AMPL Solution: maxdel = 7222211111111111133229/20/05 ELEC 5970-001/6970-001 Lecture 8 22AMPL Solution: maxdel ≥ 112233111111114433559/20/05 ELEC 5970-001/6970-001 Lecture 8 23Original 1-Bit AdderColor codes for number of transitions9/20/05 ELEC 5970-001/6970-001 Lecture 8 24Optimized 1-Bit AdderColor codes for number of transitions9/20/05 ELEC 5970-001/6970-001 Lecture 8 25Results: 1-Bit AdderSimulated over all possible vector transitions•Average power = optimized/unit delay= 244 / 308 = 0.792•Peak power = optimized/unit delay= 6 / 10 = 0.60Power Savings : Peak = 40 % Average = 21 %9/20/05 ELEC 5970-001/6970-001 Lecture 8 26References•E. Jacobs and M. Berkelaar, “Using Gate Sizing to Reduce Glitch Power,” Proc. ProRISC/IEEE Workshop on Circuits, Systems and Signal Processing, Nov. 1996, pp. 183-188; also Int. Workshop on Logic Synthesis, May 1997.•V. D. Agrawal, “Low-Power Design by Hazard Filtering,” Proc. 10th Int. Conf. VLSI Design, Jan. 1997, pp. 193-197.•V. D. Agrawal, M. L. Bushnell, G. Parthasarathy, and R. Ramadoss, “Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method,” Proc. 12th Int. Conf. VLSI Design, Jan. 1999, pp. 434-439.•Last two papers are available at website http://www.eng.auburn.edu/~vagrawal9/20/05 ELEC 5970-001/6970-001 Lecture 8 27A Limitation•Constraints are written by path enumeration.•Since number of paths in a circuit can be exponential in circuit size, the formulation is