ELEC 5970-001/6970-001(Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits Test PowerTest Power ProblemTesting Differs from FunctionBasic Mode of TestingFunctional Inputs vs. Test VectorsAn ExampleReducing Comb. Test PowerTraveling Salesperson ProblemScan TestingExample: State MachineScan Testing of State MachineLow Power Scan Flip-FlopBuilt-In Self-Test (BIST)Test Scheduling ExampleBIST Configuration 1: Test TimeBIST Configuration 2: Test PowerTesting of MCM and SOCResource Allocation GraphTest Compatibility Graph (TCG)Test Scheduling AlgorithmTest Scheduling Algorithm . . .TS Algorithm: Cover TableA System Example: ASIC Z*Test Scheduling for ASIC ZReferences11/17/05 ELEC 5970-001/6970-001 Lecture 20 1ELEC 5970-001/6970-001(Fall 2005)Special Topics in Electrical EngineeringLow-Power Design of Electronic CircuitsTest PowerVishwani D. AgrawalJames J. Danaher ProfessorDepartment of Electrical and Computer EngineeringAuburn Universityhttp://www.eng.auburn.edu/[email protected]/17/05 ELEC 5970-001/6970-001 Lecture 20 2Test Power Problem•A circuit is designed for certain function. Its design must allow the power consumption necessary to execute that function.•Power buses are laid out to carry the maximum current necessary for the function.•Heat dissipation of package conforms to the average power consumption during the intended function.11/17/05 ELEC 5970-001/6970-001 Lecture 20 3Testing Differs from FunctionVLSI chipsystemSysteminputsSystemoutputsFunctional inputsFunctional outputsOther chips11/17/05 ELEC 5970-001/6970-001 Lecture 20 4Basic Mode of TestingVLSI chipTest vectors:Pre-generated and stored inATEDUT output for comparison with expected response stored in ATEAutomatic Test Equipment (ATE):Control processor, vector memory,timing generators, power module,response comparatorPowerClockPackaged or unpackaged device under test (DUT)11/17/05 ELEC 5970-001/6970-001 Lecture 20 5Functional Inputs vs. Test Vectors•Functional inputs:•Functionally meaningful signals•Generated by circuitry•Restricted set of inputs•May have been optimized to reduce logic activity and power•Test vectors:•Functionally irrelevant signals•Generated by software to test faults•Can be random or pseudorandom•May be optimized to reduce test time; can have high logic activity•May use testability logic for test application11/17/05 ELEC 5970-001/6970-001 Lecture 20 6An ExampleVLSI chipBinary to decimal converter3-bit random vectors8-bit1-hot vectorsVLSI chipsystemVLSI chip in system operationVLSI chip under testHigh activity8-bit test vectors from ATE11/17/05 ELEC 5970-001/6970-001 Lecture 20 7Reducing Comb. Test Power 1 1 0 0 01 0 1 0 01 0 1 0 11 0 1 1 1V1 V2 V3V4 V53 413223211V1 V2 V3 V4 V510 input transitionsTraveling salesperson problem (TSP): Find the shortest distance closed path (or cycle) to visit all nodes exactly once.V1 V3 V5 V4 V21 0 0 0 11 1 0 0 01 1 1 0 01 1 1 1 05 input transitions11/17/05 ELEC 5970-001/6970-001 Lecture 20 8Traveling Salesperson Problem•A. V. Aho, J. E. Hopcroft anf J. D. Ullman, Data Structures and Algorithms, Reading, Massachusetts: Addison-Wesley, 1983.•E. Horowitz and S. Sahni, Fundamentals of Computer Algorithms, Computer Science Press, 1984.11/17/05 ELEC 5970-001/6970-001 Lecture 20 9Scan TestingCombinational logicScan flip- flopsPrimary inputsPrimary outputsScan-inSIScan-outSOScan enableSEDFFmuxSESIDDD’D’SO1011/17/05 ELEC 5970-001/6970-001 Lecture 20 10Example: State MachineS5S1S4S2S3Reduced power state encodingS1 = 000S2 = 011S3 = 001S4 = 010S5 = 100State transitionComb. Input changes000 → 001 1000 → 100 1011 → 010 1001 → 011 1010 → 000 1100 → 010 2Functional transitions11/17/05 ELEC 5970-001/6970-001 Lecture 20 11Scan Testing of State MachineCombinational logicFF=0FF=0FF=1Primary inputsPrimary outputsScan-in010Scan-out100State transitionComb. Input changes100 → 010 2010 → 101 3101 → 010 3Test transitions11/17/05 ELEC 5970-001/6970-001 Lecture 20 12Low Power Scan Flip-FlopDFFmuxSESIDDFFmuxSESIDSOD’D’SOScan FF cell Low power scan FF cell1011/17/05 ELEC 5970-001/6970-001 Lecture 20 13Built-In Self-Test (BIST)Linear feedback shift register (LFSR)Multiple input signature register (MISR)Circuit under test (CUT)Pseudo-random patternsCircuit responsesBISTControllerClockC. E. Stroud, A Designer’s Guide to Built-In Self-Test, Boston: KluwerAcademic Publishers, 2002.11/17/05 ELEC 5970-001/6970-001 Lecture 20 14Test Scheduling ExampleR1 R2M1M2R3 R4A datapath11/17/05 ELEC 5970-001/6970-001 Lecture 20 15BIST Configuration 1: Test TimeLFSR1 LFSR2M1M2MISR1 MISR2Test timeTest power T1: test for M1T2: test for M211/17/05 ELEC 5970-001/6970-001 Lecture 20 16BIST Configuration 2: Test PowerR1 LFSR2M1M2MISR1 MISR2Test timeTest power T1: test for M1T2: test for M211/17/05 ELEC 5970-001/6970-001 Lecture 20 17Testing of MCM and SOC•Test resources: Typically registers and multiplexers that can be reconfigured as test pattern generators (e.g., LFSR) or as output response analyzers (e.g., MISR).•Test resources (R1, . . . ) and tests (T1, . . . ) are identified for the system to be tested.•Each test is characterized for test time, power dissipation and resources it requires.11/17/05 ELEC 5970-001/6970-001 Lecture 20 18Resource Allocation GraphT1 T2 T3 T4 T5 T6R2R1 R3 R4 R5 R6 R7 R8 R911/17/05 ELEC 5970-001/6970-001 Lecture 20 19Test Compatibility Graph (TCG)T1(2, 100)T2(1,10)T3(1, 10)T4(1, 5)T5(2, 10)T6(1, 100)Tests that form a clique can be performed concurrently.PowerTest timePmax = 411/17/05 ELEC 5970-001/6970-001 Lecture 20 20Test Scheduling Algorithm•Identify all possible cliques in TCG:•C1 = {T1, T3, T5}•C2 = {T1, T3, T4}•C3 = {T1, T6}•C4 = {T2, T5}•C5 = {T2, T6}•Break up clique sets into power compatible sets (PCS), that satisfy the power constraint.11/17/05 ELEC 5970-001/6970-001 Lecture 20 21Test Scheduling Algorithm . . .•PCS (Pmax = 4), tests within a set are ordered for decreasing test length:•C1 = {T1, T3, T5} → (T1, T3), (T1, T5), (T3, T5)•C2 = {T1, T3, T4} → (T1, T3, T4)•C3 = {T1, T6} → (T1, T6)•C4 = {T2, T5} → (T2, T5)•C5 = {T2, T6} → (T2, T6)•Expand PCS into subsets of decreasing test lengths. Each subset is an independent test session, consisting of tests that can be concurrently applied.•Select test sessions to cover all tests such that the added
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