ELEC 5970-001/6970-001(Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits Adiabatic and Charge Recovery LogicExamples of Power Saving and Energy RecoveryReexamine CMOS GateCharging with Constant CurrentOr, Charge in StepsEnergy Dissipation of a StepCharge in N StepsReferencesDynamic CMOS InverterAdiabatic Dynamic CMOS InverterCascaded Adiabatic InvertersComplex ADL GateQuasi-Adiabatic LogicQuasi-Adiabatic Logic DesignA Case StudyQuasi-Adiabatic 32-bit ARM Based Microprocessor Design SpecificationsTechnology DistributionPower AnalysisPower Analysis (Cont’d.)Area AnalysisSummary10/27/05 ELEC 5970-001/6970-001 Lecture 16 1ELEC 5970-001/6970-001(Fall 2005)Special Topics in Electrical EngineeringLow-Power Design of Electronic CircuitsAdiabatic and Charge Recovery LogicVishwani D. AgrawalJames J. Danaher ProfessorDepartment of Electrical and Computer EngineeringAuburn Universityhttp://www.eng.auburn.edu/[email protected]/27/05 ELEC 5970-001/6970-001 Lecture 16 2Examples of Power Saving and Energy Recovery•Power saving by power transmission at high voltage:–1000W transmitted at 100V, current I = 10A–If resistance of transmission circuit is 1Ω, then power loss = I2R = 100W–Transmit at 1000V, current I = 1A, transmission loss = 1W•Energy recovery from automobile brakes:–Normal brake converts mechanical energy into heat–Instead, the energy can be stored in a flywheel, or–Converted to electricity to charge a battery10/27/05 ELEC 5970-001/6970-001 Lecture 16 3Reexamine CMOS Gate i = Ve-t/RpC/Rp i2RpVV2/RpCTime, tPowerMost energy dissipated hereV2e-2t/RpC/Rp0Energy = Area = CV2/2 v(t)V v(t) v(t)3RpC10/27/05 ELEC 5970-001/6970-001 Lecture 16 4Charging with Constant Current i = K i2RpV(t)CPower0 v(t) = Kt/CTime to charge capacitor to voltage V v(T) = V = KT/C, or T = CV/KCurrent, i = K = CV/TOutput voltage, v(t)0VTime, t t=CV/KKt/CPower = i2Rp = C2V2Rp/T2Energy = Power × T = (RpC/T) CV2 C2V2Rp/T210/27/05 ELEC 5970-001/6970-001 Lecture 16 5Or, Charge in Steps i = Ve-t/RpC/2Rp i2Rp0→V/2→VV2/4RpCTime, tPowerV2e-2t/RpC/4Rp0Energy = Area = CV2/8 v(t)V v(t) v(t)V/2Total energy = CV2/8 + CV2/8 = CV2/43RpC 6RpC10/27/05 ELEC 5970-001/6970-001 Lecture 16 6Energy Dissipation of a Step TE = ∫ V2e-2t/RpC/(N2Rp) dt 0 = [CV2/(2N2)] (1 – e-2T/RpC) ≈ CV2/(2N2) for large T ≥ 3RpCVoltage step = V/N10/27/05 ELEC 5970-001/6970-001 Lecture 16 7Charge in N StepsSupply voltage 0 → V/N → 2V/N → 3V/N → . . . NV/NCurrent, i(t) = Ve-t/RpC/NRpPower, i2(t)Rp = V2e-2t/RpC/N2RpEnergy = N CV2/2N2 = CV2/2N → 0 for N → ∞Delay = N × 3RpC → ∞ for N → ∞10/27/05 ELEC 5970-001/6970-001 Lecture 16 8References•C. L. Seitz, A. H. Frey, S. Mattisson, S. D. Rabin, D. A. Speck and J. L. A. van de Snepscheut, “Hot-Clock nMOS,” Proc. Chapel Hill Conf. VLSI, 1985, pp. 1-17.•W. C. Athas, L. J. Swensson, J. D. Koller, N. Tzartzanis and E. Y.-C. Chou, “Low-Power Digital Systems Based on Adiabatic-Switching Principles,” IEEE Trans. VLSI Systems, vol. 2, no. 4, pp. 398-407, Dec. 1994.10/27/05 ELEC 5970-001/6970-001 Lecture 16 9Dynamic CMOS InverterVC v(t)CK vinCK vin v(t)P E P E P E10/27/05 ELEC 5970-001/6970-001 Lecture 16 10Adiabatic Dynamic CMOS InverterC v(t)CK vinA. G. Dickinson and J. S. Denker, “Adiabatic Dynamic Logic,” IEEE J. Solid-State Circuits, vol. 30, pp. 311-315, March 1995.CK vin v(t)V0V-Vf0Vf+10/27/05 ELEC 5970-001/6970-001 Lecture 16 11Cascaded Adiabatic InvertersCK1 CK2 CK1’ CK2’ vinCK1CK2CK1’CK2’prechargeinputevaluatehold10/27/05 ELEC 5970-001/6970-001 Lecture 16 12Complex ADL GateCK BA. G. Dickinson and J. S. Denker, “Adiabatic Dynamic Logic,” IEEE J. Solid-State Circuits, vol. 30, pp. 311-315, March 1995.ACAB + CVf < Vth10/27/05 ELEC 5970-001/6970-001 Lecture 16 13Quasi-Adiabatic Logic•Two sets of diodes: One controls the charging path (D1) while the other (D2) controls the discharging path•Supply lines have EVALUATE phase ( swings up) and HOLD phase ( swings low)D1D210/27/05 ELEC 5970-001/6970-001 Lecture 16 14Possible Cases:•The circuit output node X is LOW and the pMOS tree is turned ON: X follows  as it swings to HIGH (EVALUATE phase)•The circuit node X is LOW and the nMOS tree is ON. X remains LOW and no transition occurs (HOLD phase)•The circuit node X is HIGH and the pMOS tree is ON. X remains HIGH and no transition occurs (HOLD phase)•The circuit node X is HIGH and the nMOS tree is ON. X follows  down to LOW, i.e. energy is recovered (RESTORE phase)Quasi-Adiabatic Logic Design10/27/05 ELEC 5970-001/6970-001 Lecture 16 15A Case StudyK. Parameswaran, “Low Power Design of a 32-bit Quasi-Adiabatic ARM Based Microprocessor,” Master’s Thesis,Dept. of ECE, Rutgers University, New Brunswick, NJ, 2004.10/27/05 ELEC 5970-001/6970-001 Lecture 16 16Quasi-Adiabatic 32-bit ARM Based Microprocessor Design Specifications•Operating voltage: 2.5 V•Operating temperature: 25oC•Operating frequency: 10 MHz to 100 MHz•Leakage current: 0.5 fAmps•Load capacitance: 6X10-18 F (15% activity)•Transistor Count10/27/05 ELEC 5970-001/6970-001 Lecture 16 17Technology Distribution•Microprocessor has a mix of static CMOS and Quasi-adiabatic componentsALUALU• Adder-subtractor unit• Barrel shifter unit• Booth-multiplier unit ALUALU• Adder-subtractor unit• Barrel shifter unit• Booth-multiplier unit Control UnitsControl Units• ARM controller unit• Bus control unitPipeline UnitsPipeline Units• ID unit• IF unit• WB unit• MEM unitControl UnitsControl Units• ARM controller unit• Bus control unitPipeline UnitsPipeline Units• ID unit• IF unit• WB unit• MEM unitQuasi-Adiabatic Static CMOS10/27/05 ELEC 5970-001/6970-001 Lecture 16 18Power AnalysisDatapathComponentPower Consumption (mW)Frequency 25 MHzPower Consumption (mW)Frequency 100 MHzQuasi-adiabatic* Static CMOSPower SavedQuasi-adiabatic* Static CMOSPower Saved32-bit Adder Subtracter1.01 1.55 44% 1.29 1.62 20%32-bit Barrel Shifter0.9 1.681 46% 1.368 1.8 24%32-bit Booth Multiplier3.4 5.8 40% 5.15 6.2 17%Power Consumption (mW)Frequency 25 MHzQuasi-adiabatic* Static CMOSPower Saved60 mW 85 mW 40%10/27/05 ELEC 5970-001/6970-001 Lecture 16 19Power Analysis (Cont’d.)10/27/05 ELEC 5970-001/6970-001 Lecture 16 20Area AnalysisDatapathComponentArea (mm2)Quasi-adiabatic* Static CMOS Area Increase32-bit Adder Subtracter 0.05 0.03