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AUBURN ELEC 5970 - Power Analysis: High-Level

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ELEC 5970-001/6970-001(Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits Power Analysis: High-LevelKey ParametersArchitecture-Level Power EstimationA Complexity-Based ModelImproving Complexity ModelsAn On-Chip SRAMPower Consumed by SRAMActivity-Based ModelsBinary SignalsEntropy and ActivityEntropy of a CircuitInput and Output EntropyAverage AcrivityArea EstimatePowerSequential CircuitEmpirical MethodsExample: RISC MicroprocessorAdditional References10/13/05 ELEC 5970-001/6970-001 Lecture 13 1ELEC 5970-001/6970-001(Fall 2005)Special Topics in Electrical EngineeringLow-Power Design of Electronic CircuitsPower Analysis: High-LevelVishwani D. AgrawalJames J. Danaher ProfessorDepartment of Electrical and Computer EngineeringAuburn Universityhttp://www.eng.auburn.edu/[email protected]/13/05 ELEC 5970-001/6970-001 Lecture 13 2Key Parameters•Capacitance–Area–Complexity•Activity–Dynamic behavior–Operational characteristicsPower α Capacitance × Activity10/13/05 ELEC 5970-001/6970-001 Lecture 13 3Architecture-Level Power Estimation•Analytical methods–Complexity-based models–Activity-based models•Empirical methods–Fixed-activity models–Activity-sensitive models10/13/05 ELEC 5970-001/6970-001 Lecture 13 4A Complexity-Based Modelwhere•GEk = gate equivalent count for block k, e.g., estimated number of 2-input NANDs.•Etyp = average energy consumed by an active typical 2-input NAND.•CLk = average capacitance of a gate in block k.• f = clock freqency.•VDD= supply voltage.•Ak= average fraction of gates switching in block k.Power = Σ GEk (Etyp + CLkVDD2) f Ak All functional blocks kRef.: K. Müller-Glaser, K. Kirsch and K. Neusinger, “Estimating EssentialDesign Characteristics to Support Project Planning for ASIC DesignManagement,” Proc. IEEE Int. Conf. CAD, Nov. 1991, pp. 148-151.10/13/05 ELEC 5970-001/6970-001 Lecture 13 5Improving Complexity Models•Treat logic, memory, interconnects and clock tree, separately•For example, a memory array may not be modeled as equivalent NAND gates, but as a memory cell.10/13/05 ELEC 5970-001/6970-001 Lecture 13 6Memory arrayAn On-Chip SRAMSense and column decodeRow decode and driversCtrlAddress bus. . .. . .. . .. . .Data bus word line bit lineSix-transistor memory cell2k cells2n-k cells10/13/05 ELEC 5970-001/6970-001 Lecture 13 7Power Consumed by SRAM 2k Power = ── (cint lcol +2n-k ctr) VDD Vswing f 2Where 2knumber of cells in a rowcintwire capacitance per unit lengthlcolmemory column length2n-knumber of cells in a columnctrminimum size transistor drain capacitanceVswingbitline voltage swingRef.: D. Liu and C. Svenson, “Power Consumption Estimation inCMOS VLSI Chips,” IEEE J. Solid-State Circuits, June 1991,pp. 663-670.10/13/05 ELEC 5970-001/6970-001 Lecture 13 8Activity-Based Models•Power α capacitance × activity•Capacitance α area•Both area and activity can be estimated from the entropy of a Boolean function.•Definition: Entropy of a system with m states having probabilities p1, p2, . . . , pm, is mH = - Σ pk log2 pk bitsk=110/13/05 ELEC 5970-001/6970-001 Lecture 13 9Binary Signals•Entropy of a binary signal: H(p1) = - p1 log2 p1 – (1- p1) log2(1-p1)•Entropy of an n-bit binary vector:nH(X) = Σ H(p1k)k=110/13/05 ELEC 5970-001/6970-001 Lecture 13 10Entropy and Activityp1k0.0 0.25 0.5 0.75 1.01.00.750.500.250.0Entropy4 p1k(1-p1k)10/13/05 ELEC 5970-001/6970-001 Lecture 13 11Entropy of a CircuitCombinationalLogic...X1X2Xn...Y1Y2Ym10/13/05 ELEC 5970-001/6970-001 Lecture 13 12Input and Output Entropy2nHi = Σ pk log2 pkk=1 where pk = probability of kth input vector2mHo = Σ pj log2 pjj=1 where pj = probability of jth output vector10/13/05 ELEC 5970-001/6970-001 Lecture 13 13Average AcrivityHiHoCircuit depth →PI PO 2/3Average entropy ≈ ─── (Hi + 2Ho)n+mQuadratic decayHi ≥ Ho10/13/05 ELEC 5970-001/6970-001 Lecture 13 14Area Estimate•K.-T. Cheng and V. D. Agrawal, “An Entropy Measure for the Complexity of Multi-Output Boolean Functions,” Proc. 17th DAC, 1990, pp. 302-305.•M. Nemani and F. Najm, “Towards a High-Level Power Estimation Capability,” IEEE Trans. CAD, vol. 15, no. 6, pp. 588-598, June 1996.Area = 2n Ho/n for large n= 2n Ho for n ≤ 1010/13/05 ELEC 5970-001/6970-001 Lecture 13 15PowerNPower = K1 × Av. Activity × Σ Ck = K2 × Av. Activity × Areak=1 where Ck is the capacitance of kth node in a circuit with N nodes 2n+1Power = K3 ────── Ho (Hi + Ho) 3n(n+m)Constant K3 is determined by simulation of gate-level circuits.10/13/05 ELEC 5970-001/6970-001 Lecture 13 16Sequential CircuitCombinationalLogicFlip-flopsPI POHiHoHi and Ho are determined from high-level simulation.10/13/05 ELEC 5970-001/6970-001 Lecture 13 17Empirical Methods•Functional blocks are characterized for power consumption in active and inactive (standby) modes by–Analytical methods, or–Simulation, or–Measurement•A software simulator determined which blocks become active and adds their power consumption.10/13/05 ELEC 5970-001/6970-001 Lecture 13 18Example: RISC Microprocessor IF ID EX MEM WB IF ID EX MEM WB add R1←R2+R3 lw R4←4(R5)Clock cycles 1 2 3 4 5 6 . . . mem rfile ALU rfile pcadd braddmem rfile ALU mem rfilepcadd bradd mem ALUrfile memALUALUALU ALU rfile rfileALUrfilememtimePowerprofile10/13/05 ELEC 5970-001/6970-001 Lecture 13 19Additional References•P. E. Landman, “A Survey of High-Level Power Estimation Techniques,” in Low-Power CMOS Design, A. Chandrakasan and R. Brodersen (Editors), New York: IEEE Press, 1998.•P. E. Landman and J. M. Rabaey, “Activity-Sensitive Architectural Power Analysis,” IEEE Trans. CAD, vol. 15, no. 6, pp. 571-587, June


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