ELEC 5970-001/6970-001(Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits Low Voltage Low Power DevicesThreshold Voltage, VtBulk nMOSFETα-Power Law Modelα-Power Law Model (Cont.)Slide 6Slide 7Power and DelayPower-Delay ProductOptimum Threshold VoltageLeakageLeakage Current ComponentsSubthreshold LeakageNormal CMOS InverterLeakage Reduction by Body BiasBody Bias, VBBnFurther on Body BiasSummary9/01/05 ELEC5970-001/6970-001 Lecture 4 1ELEC 5970-001/6970-001(Fall 2005)Special Topics in Electrical EngineeringLow-Power Design of Electronic CircuitsLow Voltage Low Power DevicesVishwani D. AgrawalJames J. Danaher ProfessorDepartment of Electrical and Computer EngineeringAuburn Universityhttp://www.eng.auburn.edu/[email protected]/01/05 ELEC5970-001/6970-001 Lecture 4 2Threshold Voltage, Vt +-0 < Vg < Vt+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Depletion regionPolysilicon gateSiO2 p-type body +-Vg > Vt+ + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - -Depletion region+ + + + + + + + + + + + ++ + + + + + + + + + + + +Polysilicon gateSiO2 p-type bodyVt is a function of:Dopant concentrationThickness of oxide9/01/05 ELEC5970-001/6970-001 Lecture 4 3Bulk nMOSFET n+ p-type body (bulk) n+LWSiO2Thickness = toxGateSourceDrainPolysiliconVgsVgd9/01/05 ELEC5970-001/6970-001 Lecture 4 4 α-Power Law ModelVgs > Vt and Vds > Vdsat = Vgs –Vt (Saturation region): βIds= Pc ─ (Vgs – Vt)α 2 where β = μCoxW/LFor fully ON transistor, Vgs = Vds = VDD: βIdsat= Pc ─ (VDD – Vt)α 2T. Sakurai and A. R. Newton, “Alpha-Power Law MOSFET Model and Its Applications to CMOS Inverter Delay and Other Formulas,”IEEE J. Solid State Circuits, vol. 25, no. 2, pp. 584-594, 1990.9/01/05 ELEC5970-001/6970-001 Lecture 4 5α-Power Law Model (Cont.)Vgs = 1.8VShockley α-power lawSimulationVdsIds (μA)0 0.3 0.6 0.9 1.2 1.5 1.8400300200100 0Idsat9/01/05 ELEC5970-001/6970-001 Lecture 4 6α-Power Law Model (Cont.)0 Vgs < Vt, cutoff Ids= Idsat×Vds/VdsatVds < Vdsat, linearIdsatVds >Vdsat, saturationVdsat= Pv(Vgs – Vt)α/29/01/05 ELEC5970-001/6970-001 Lecture 4 7α-Power Law Model (Cont.)• α = 2, for long channel devices or low VDD• α ~ 1, for short channel devices9/01/05 ELEC5970-001/6970-001 Lecture 4 8Power and DelayPower = CVDD2CVDD 1 1Inverter delay = ──── (─── + ─── ) 4 Idsatn Idsatp KVDD= ───────(VDD – Vt)α9/01/05 ELEC5970-001/6970-001 Lecture 4 9Power-Delay Product VDD3Power × Delay = constant × ─────── (VDD – Vt)α0.6V 1.8V 3.0V VDDPowerDelay9/01/05 ELEC5970-001/6970-001 Lecture 4 10Optimum Threshold VoltageFor minimum power-delay product: 3VtVDD= ───3 – αFor long channel devices, α = 2, VDD = 3VtFor very short channel devices, α = 1, VDD = 1.5Vt9/01/05 ELEC5970-001/6970-001 Lecture 4 11LeakageIGIDIsubIPTIGIDLn+ n+GroundVDDR9/01/05 ELEC5970-001/6970-001 Lecture 4 12Leakage Current Components•Subthreshold conduction, Isub•Reverse bias pn junction conduction, ID•Gate induced drain leakage, IGIDL due to tunneling at the gate-drain overlap•Drain source punchthrough, IPT due to short channel and high drain-source voltage•Gate tunneling, IG through thin oxide9/01/05 ELEC5970-001/6970-001 Lecture 4 13Subthreshold LeakageVgs – Vt Isub = I0 exp( ───── ) nvth0 0.3 0.6 0.9 1.2 1.5 1.8 V VgsIds1mA100μA10μA1μA100nA10nA1nA100pA10pAVtSubthresholdregionSaturation region9/01/05 ELEC5970-001/6970-001 Lecture 4 14Normal CMOS InverterPolysilicon (input)SiO2 p+ n+ n+ p+ p+ n+ n-well p-substrate (bulk) metal 1VDDGND output input outputVDDGNDo9/01/05 ELEC5970-001/6970-001 Lecture 4 15Leakage Reduction by Body BiasPolysilicon (input)SiO2 p+ n+ n+ p+ p+ n+ n-well p-substrate (bulk) metal 1VDDGND output input outputVBBpVDDGNDVBBnVBBnVBBpo9/01/05 ELEC5970-001/6970-001 Lecture 4 16Body Bias, VBBn +-0 < Vg < Vt+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Depletion regionPolysilicon gateSiO2 p-type body +-Vg < 0- - - - - - - - - - - - - - - - - - + + + + + + + + + + + + ++ + + + + + + + + + + + ++ + + + + + + + + + + + ++ + + + + + + + + + + + +Polysilicon gateSiO2 p-type bodyVt is a function of:Dopant concentrationThickness of oxide9/01/05 ELEC5970-001/6970-001 Lecture 4 17Further on Body Bias•Large body bias can increase gate leakage (IG) via tunneling through oxide.•Body bias is kept less than 0.5V.•For VDD = 1.8V:•VBBn = -0.4V•VBBp = 2.2V9/01/05 ELEC5970-001/6970-001 Lecture 4 18Summary•Device scaling down reduces supply voltage–Reduced power–Increases delay•Optimum power-delay product by scaling down threshold voltage•Threshold voltage reduction increases subthreshold leakage power–Use body bias to reduce subthreshold leakage–Body bias may increase gate
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