AUBURN ELEC 5970 - Impact of Pass-Transistor Logic (PTL) (6 pages)

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Impact of Pass-Transistor Logic (PTL)



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Impact of Pass-Transistor Logic (PTL)

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Pages:
6
School:
Auburn University
Course:
Elec 5970 - SPECIAL TOPICS IN ELECTRICAL ENGINEERING (1-5)

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Impact of Pass Transistor Logic PTL on Power Delay and Area Kalyana R Kantipudi ECE Department Auburn University Low Power VLSI Design Fall 05 Abstract Power reduction is a serious concern now days As the MOS devices are wide spread there is high need for circuits which consume less power mainly for portable devices which run on batteries like Laptops and hand held computers The PassTransistor Logic PTL is a better way to implement circuits designed for low power applications Introduction The power consumption in a circuit can be decreased by reducing Switching activity in the circuit Switching capacitance of each node Supply voltage Short Circuit Current Let s look at a PTL design L W 0 A B AB AB A This kind of PTL design is called the Single Rail Pass Transistor Logic also called LEAP Here a basic AND NAND function is implemented The PMOS transistor which is connected opposite to the output inverter is called a bleeder transistor which is used to pull the weak 1 arriving at the input of the inverter Now the advantage of PTL comes from the fact that it is best suitable to implement all the above power reduction techniques 1 Switching activity in the circuit can be reduced by eliminating the glitches This can be done by controlling the delays of each pass transistor controlling the widths and lengths 2 Switching capacitance of a node in the PTL will be less when compared to a node in the CMOS design Due to the smaller size of the transistors in PTL implementation The lengths of the transistors should be as small as possible because increased lengths result in more IRdrop across the transistor The widths of transistors also should be small It s because the improvement seen in the switching of that transistor will be subdued by the delay caused in the input which is driving that wider gate This phenomenon can be observed in the presentation slides 3 Like the CMOS technologies the supply voltage can be reduced at the cost of some increase in delay of the circuit 4



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