Impact of Pass-Transistor Logic (PTL) on Power, Delay and AreaOutline:Introduction:What Can We Reduce?What PTL Can Offer?The Catch…PTL Logic Formulation and Implementation:Slide 8Why 250nm Instead Of 180nm TechnologyTrade-offs Needed Delay due to load Vs. Delay due to gateTrade-offs needed Delay due to load Vs. Delay due to gateTransmission GateThe AND Gate:How to get to those features:Regarding the Robustness of Tx GateA New XOR Design is Invented[4]The New “multi_cell” Design[5]The Waveforms Circuit specifications:Regarding The Area Specs.Conclusions:References:Dec. 1, 2005 ELEC 6970-001 Class Presentation1Impact of Pass-Transistor Logic (PTL) on Power, Delay and AreaKalyana R KantipudiECE DepartmentAuburn UniversityDec. 1, 2005 ELEC 6970-001 Class Presentation2Outline:IntroductionPros & Cons of PTLA PTL DesignNeed for an Improved DesignA Transmission gate DesignA new improved PTL DesignConclusionsDec. 1, 2005 ELEC 6970-001 Class Presentation3Introduction:The power equation:Ptotal = CLVDD2 + TscVDDIpeak + VDDIleakagePdyn = VDD2fclk.Σn.cn + VDD.ΣIsc nPleakage = VDDIsubleakage = μ0 Cox (W/L) Vt2 exp{(VGS-VTH)/nVt}Dec. 1, 2005 ELEC 6970-001 Class Presentation4What Can We Reduce?Activity in the circuitSwitching capacitance1. Reducing Width and LengthSupply voltage reductionShort-circuit reductionDec. 1, 2005 ELEC 6970-001 Class Presentation5What PTL Can Offer?One pass-transistor network is enough.Reduction in number of transistors.Decrease in width and length of transistors.Results in smaller ‘input’ and ‘driving’ loads.Dec. 1, 2005 ELEC 6970-001 Class Presentation6The Catch…Reduction in level of the signal (VDD-Vth-IR).1. Needs level restoration at gate outputs in order to avoid static currents.2. Adjust threshold voltages (Vthp > Vthn).Only one single path through each network must be active at a time. (To avoid shorts between the inputs)1. A multiplexer kind of structure is to be implemented all the time.Dec. 1, 2005 ELEC 6970-001 Class Presentation7PTL Logic Formulation and Implementation:Dec. 1, 2005 ELEC 6970-001 Class Presentation8Dec. 1, 2005 ELEC 6970-001 Class Presentation9Why 250nm Instead Of 180nm TechnologyVDD - VTpVoltVDDVi(t)Vo(t)VTnFor 180 nm: Vthn=0.51V Vthp=-0.52VIf a pass transistor is feeding an inverter:Vin(inv) = VDD – Vthn – IRdrop = 1.8 – 0.51 – 0.2 = 1.09 VBut for the p-transistor in an inverter to switch-OFF, the Vin should be atleast (VDD – |Vthp| = 1.28 V)Other solutions:1. Keep Vthn of the NMOS pass transistors as low as possible.2. Keep Vthp of the inverter higher than Vthn.Dec. 1, 2005 ELEC 6970-001 Class Presentation10Trade-offs Needed Delay due to load Vs. Delay due to gateWidths of the pass transistors: 30-9-7-5-3-1Dec. 1, 2005 ELEC 6970-001 Class Presentation11Trade-offs needed Delay due to load Vs. Delay due to gateWidths of the pass transistors: 30-9-7-5-3-7/3-7/7-1Dec. 1, 2005 ELEC 6970-001 Class Presentation12Transmission GateMaintains the voltage swing of the signalStrong ‘1’ and strong ‘0’.As there are two channels conducting, the device speed improves.It is found that the transmission gate has robust characteristics compared to a CMOS gate.Dec. 1, 2005 ELEC 6970-001 Class Presentation13The AND Gate:CMOS AND gate:Static Power: 31.1411 pWDynamic Power: 1.8285 uWCritical Delay: 214 pico secs.TX gate based AND:Static Power: 43.177 pWDynamic Power: 417.863 nWCritical Delay: 172 pico secs.Dec. 1, 2005 ELEC 6970-001 Class Presentation14How to get to those features:Parameters:Lpass_p/Lpass_nWp/Lp,Wn/LnStatic PowerDynamic PowerDelayin Pico secs.(1/1,9/2,5/2) 59.88pW 618.57nW 173(1/1,1/1,1/1) 4.42uW 24.01uW 184(1/1,3/1,2/1) 2.67nW 32.03uW 145(1/1,3/2,2/2) 146.54pW 368.18nW 184(1/1,6/2,3/3) 43.17pW 417.86nW 172(4/2,6/2,3/3) 43.18pW 1.07uW 366(2/2,6/2,3/3) 43.18pW 609.96nW 260Dec. 1, 2005 ELEC 6970-001 Class Presentation15Regarding the Robustness of Tx GateGate Status Static PowerDynamic PowerDelayin Pico secs.CMOS Without any load31.14pW 1.83uW 214Feeding an inverter78.49pW 2.14uW 257.5Tx gateWithout any load43.17pW 417.86nW 172Feeding an inverter80.31pW 960.32nW 238.2The Tx gate based “multi_cell” implementation is in progress >>Dec. 1, 2005 ELEC 6970-001 Class Presentation16A New XOR Design is Invented[4]Dec. 1, 2005 ELEC 6970-001 Class Presentation17The New “multi_cell” Design[5]In this new design, the entire “Multi_cell” needs just 15 transistors.Most of the transistors will be in their minimum size.Questions:Will it work ???Does it has the drive capability ?Dec. 1, 2005 ELEC 6970-001 Class Presentation18The Waveforms Dec. 1, 2005 ELEC 6970-001 Class Presentation19Circuit specifications:Circuit Type Static PowerDynamic PowerDelayPTL353.36pW79.24uW 8.45nsCMOS356.56pW12.49uW 551psNew PTL 105.15pW16.63uW 662psDec. 1, 2005 ELEC 6970-001 Class Presentation20Regarding The Area Specs.CMOS has 38 transistors while the PTL has 39 transistors (most of the transistors having minimum feature size).Considering the ( ΣLW ) the area of CMOS cell is (960□/233□ = 4.12) times the size of the PTL cell.Dec. 1, 2005 ELEC 6970-001 Class Presentation21Conclusions:The area overhead of CMOS is at least 4 times more than the PTL.The power consumption is less in case of PTL compared to CMOS.A good PTL design needs a lot of astute trade-offs.Dec. 1, 2005 ELEC 6970-001 Class Presentation22References:1. J. M. Rabaey, A. Chandrakasan, B Nikolic, Digital Integrated Circuits-A Design Perspective. Prentice Hall, 2004.2. R. Zimmermann and Wolfgang Fichtner, “Low-power Logic Styles: CMOS Versus Pass-Transistor Logic,” IEEE J. Solid-State Circuits, vol.32, pp. 1079-1090, Jul. 1997.3. Geun Rae Cho, Tom Chen. "On The Impact of Technology Scaling On Mixed PTL/Static Circuits," 2002 IEEE International Conference on Computer Design (ICCD'02),p. 322,V 2002.4. Jyh-Ming Wang, Sung-Chuan Fang, Wu-Shiung Feng,“New Efficient Designs for XOR and XNOR Functions on the Transistor Level,” IEEE J. of Solid-state Circuits, Vol. 29, pp. 780-786, July 1994.5. H. T. Bui, Y. Wang, and Y. Jiang, "Design and analysis of low-power IO-transistor full adders using novel XOR-XNOR gates," IEEE Trans. on Circuits and Systems-I/: Analog and digital signal processing, vol. 49, no. 1, pp. 25-30, Jan 2002.6. H. Lee and G.E. Sobelman, “A new low-voltage adder circuit,” in Proc.