ELEC 5970-001/6970-001(Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits Power Analysis: Logic LevelPower AnalysisAbstraction, Complexity, AccuracySpiceLogic Model of MOS CircuitSpice CharacterizationSpice Characterization (Cont.)Switch-Level PartitioningDelay and Discrete-Event Simulation (NAND gate)Event-Driven Simulation (Example)Time Wheel (Circular Stack)Gate-Level Power AnalysisElmore Delay ModelElmore Delay FormulaGate-Level Power Analysis (Cont.)Slide 16Slide 17Slide 189/29/05 ELEC 5970-001/6970-001 Lecture 10 1ELEC 5970-001/6970-001(Fall 2005)Special Topics in Electrical EngineeringLow-Power Design of Electronic CircuitsPower Analysis: Logic LevelVishwani D. AgrawalJames J. Danaher ProfessorDepartment of Electrical and Computer EngineeringAuburn Universityhttp://www.eng.auburn.edu/[email protected]/29/05 ELEC 5970-001/6970-001 Lecture 10 2Power Analysis•Motivation:–Specification–Optimization–Reliability•Applications–Design analysis and optimization–Physical design–Packaging–Test9/29/05 ELEC 5970-001/6970-001 Lecture 10 3Abstraction, Complexity, AccuracyAbstraction level Computing resources Analysis accuracyAlgorithm Least WorstSoftware and systemHardware behaviorRegister transferLogicCircuitDevice Most Best9/29/05 ELEC 5970-001/6970-001 Lecture 10 4Spice•Circuit/device level analysis•Circuit modeled as network of transistors, capacitors, resistors and voltage/current sources.•Node current equations using Kirchhoff’s current law.•Average and instantaneous power computed from supply voltage and device current.•Analysis is accurate but expensive•Used to characterize parts of a larger circuit.•Original references:•L. W. Nagel and D. O. Pederson, “SPICE – Simulation Program With Integrated Circuit Emphasis,” Memo ERL-M382, EECS Dept., University of California, Berkeley, Apr. 1973.•L. W. Nagel, SPICE 2, A Computer program to Simulate Semiconductor Circuits, PhD Dissertation, University of California, Berkeley, May 1975.9/29/05 ELEC 5970-001/6970-001 Lecture 10 5Ca Logic Model of MOS CircuitCc Cb VDD a b c pMOS FETsnMOSFETsCa , Cb , Cc and Cd are node capacitancesDcDacab Da and Db are interconnect or propagation delays Dc is inertial delayof gateDbCd9/29/05 ELEC 5970-001/6970-001 Lecture 10 6Spice CharacterizationInput data pattern Delay (ps) Dynamic energy (pJ) a = b = 0 → 1 69 1.55 a = 1, b = 0 → 1 62 1.67 a = 0 → 1, b = 1 50 1.72a = b = 1 → 0 35 1.82a = 1, b = 1 → 0 76 1.39a = 1 → 0, b = 1 57 1.949/29/05 ELEC 5970-001/6970-001 Lecture 10 7Spice Characterization (Cont.)Input data pattern Static power (pW) a = b = 0 5.05 a = 0, b = 1 13.1a = 1, b = 0 5.10a = b = 1 28.59/29/05 ELEC 5970-001/6970-001 Lecture 10 8Switch-Level Partitioning•Circuit partitioned into channel-connected components for Spice characterization.•Reference: R. E. Bryant, “A Switch-Level Model and Simulator for MOS Digital Systems,” IEEE Trans. Computers, vol. C-33, no. 2, pp. 160-177, Feb. 1984.G1G2G3Internal switching nodes not seen by logic simulator9/29/05 ELEC 5970-001/6970-001 Lecture 10 9Delay and Discrete-Event Simulation (NAND gate)b ac (CMOS)Time units 05c (zero delay)c (unit delay)c (multiple delay)c (minmax delay)InputsLogic simulation min =2, max =5rise=5, fall=5Transient region Unknown (X)X9/29/05 ELEC 5970-001/6970-001 Lecture 10 10Event-Driven Simulation(Example)2242a =1 b =1c =1→0d = 0e =1f =0g =1Time, t 048gt = 0 12345678Scheduledeventsc = 0d = 1, e = 0g = 0f = 1g = 1Activitylistd, ef, ggTime stack9/29/05 ELEC 5970-001/6970-001 Lecture 10 11Time Wheel (Circular Stack)t=01234567maxCurrenttimepointerEvent link-list9/29/05 ELEC 5970-001/6970-001 Lecture 10 12Gate-Level Power Analysis•Pre-simulation analysis:–Partition circuit into channel connected gate components.–Determine node capacitances from layout analysis (accurate) or from wire-load model (approximate).–Determine dynamic and static power from Spice for each gate.–Determine gate delays using Spice or Elmore delay analysis.9/29/05 ELEC 5970-001/6970-001 Lecture 10 13Elmore Delay Model•W. Elmore, “The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers,” J. Appl. Phys., vol. 19, no.1, pp. 55-63, Jan. 1948.s12345R1R2R3R4R5C1C2C3C5C4Shared resistance:R45 = R1 + R3R15 = R1R34 = R1 + R39/29/05 ELEC 5970-001/6970-001 Lecture 10 14Elmore Delay Formula NDelay at node k = 0.69 Σ Cj × Rjk j=1 where N = number of capacitive nodes in the networkExample:Delay at node 5 = 0.69[R1 C1 + R1 C2 + (R1+R3)C3 + (R1+R3)C4 (R1+R3+R5)C5]9/29/05 ELEC 5970-001/6970-001 Lecture 10 15Gate-Level Power Analysis (Cont.)•Run discrete-event (event-driven) logic simulation with a set of input vectors.•Monitor the toggle count of each net and obtain capacitive power dissipation:Pcap= Σ CkV2 f all nodes k–Where:•Ck is the total node capacitance being switched, as determined by the simulator.•V is the supply voltage.• f is the clock frequency, i.e., the number of vectors applied per unit9/29/05 ELEC 5970-001/6970-001 Lecture 10 16Gate-Level Power Analysis (Cont.)•Monitor dynamic energy events at the input of each gate and obtain internal switching power dissipation:Pint= Σ Σ E(g,e) f(g,e) gates g events e–Where•E(g,e) = energy of event e of gate g pre-computed from Spice.•F(g,e) = occurrence frequency of the event e at gate g observed by logic simulation.9/29/05 ELEC 5970-001/6970-001 Lecture 10 17Gate-Level Power Analysis (Cont.)•Monitor the static power dissipation state of each gate and obtain the static power dissipation:Pstat= Σ Σ P(g,s) T(g,s)/ T gates g states s–Where•P(g,s) = static power dissipation of gate g for state s, obtained from Spice.•T(g,s) = duration of state s at gate g, obtained from logic simulation.•T = vector period.9/29/05 ELEC 5970-001/6970-001 Lecture 10 18Gate-Level Power Analysis (Cont.)•Sum up all three components of power:P = Pstat + Pint + Pstat•References:•A. Deng, “Power Analysis for CMOS/BiCMOS Circuits,” Proc. International Workshop Low Power Design, 1994.•J. Benkoski, A. C. Deng, C. X. Huang, S. Napper and J. Tuan, “Simulation Algorithms, Power Estimation and Diagnostics in PowerMill,” Proc. PATMOS, 1995.•C. X. Huang, B. Zhang, A. C. Deng and B. Swirski, “The Design and Implementation of PowerMill,” Proc. International Symp. Low Power Design, 1995, pp.