Delta Delay• An infinitesimally small delay.• Not a real delay. Simulation time does notadvance.• Allows for ordering of events.• Why is it needed?– Real signals never change instantaneously.– Describe hardware without ambiguities of zero-delay models. Ex. cross coupled latch.Delta delay exampleentity RS_latch is port (R, S : in bit :=‘1’; Q : buffer bit := ‘1’; Qbar :buffer bit);end RS_latch;architecture delta of RS_latch isbeginQbar <= R nand Q;Q <= S nand Qbar;end delta;configuration RS_cfg of RS_latch isfor deltaend for;end RS_cfg;Time Delta S R Q QbarEntity - Port modesin: right side of signal or variable assignment.out: left side of signal assignment.inout: both of above (for bidirectional signals)buffer: similar to inout, but can only have 1source. (Better - use internal signal forfeedback; assign it to out mode port.)Simulation - Initialization phase1. Each signal is given an initial value.Explicitly or implicitly defined.(I.e. default for bit = ‘0’, std_logic = ‘U’)2. Each process is executed until it suspends.Sensitivity list ignored first time. Each concurrent statement is executed.Simulation cycle• event-driven: signal changing value = event• simulation time advances to next event.(I.e. scheduled signal change)• Scheduled signal changes take place.• All processes (and concurrent signals)sensitive to those signals execute until theyreach a wait statement. Future eventsscheduled. Cycle repeats until no more eventsSignals Assignment vs. Variables Assignmentfrom p. 5-10 Mazor, A Guide to VHDL• Signal values arescheduled.• Signal values areupdated only afterwait is executed (canbe implicit wait). I.e.updated in nextsimulation cycle.• Signal assignmentscan have a delay.• Variable values are notscheduled.• Variable values areupdated immediately.• Variable assignmentare specified without adelay.Signals vs. Variables• VHDL - fundamentally a collection ofprocesses communicating through signals.• Signals - similar to wires in circuit.• Variables - temporary storage / intermediatevalue within processVHDL Functions• Execute in zero time. (cannot have wait)• Access only locally declared objects.• Cannot directly update signals.• Returns a single value.• Parameters of input mode.• Parameters passed as constant by default.Using Functionsprocess beginloop1: for j in 1 to 9 loopX <= Xarray(j);Y <= Yarray(j);Z <= add4 (X, Y, ‘0’);wait for 50 ns; -- Will this processend loop loop1; -- work as expected??end process;Solutions• Put Z <= add4 (X, Y, ‘0’) outside process.(I.e. make it a concurrent statement)Example - hex_7seg use in updown counter.• Put a wait for 0 ns after assignment to Y.• Pass variables to add4 rather than signals.No delta delay.Signal Drivers• Every signal assignment creates a signal driver.• Each process creates only one driver or sourcefor a signal, regardless of the number of times thesignal is assigned within the process.• A signal with more than one driver (source) musthave a resolution function associated with it;Otherwise it is an