UNIVERSITY OF CALIFORNIA, DAVIS Department of Electrical and Computer Engineering EEC180B DIGITAL SYSTEMS II Fall 1999 Lab 7-10: Micro-processor Design: Minimal Instruction Set Processor (MISP) Objective: In this lab you will design, simulate and implement a small 16-bit microprocessor. You will exercise your elementary knowledge of computer organization and you will apply your digital design knowledge and elementary skills. The processor (MISP) is given to you by its architectural specifications. Those specifications are given to you in the MISP Architecture Document that follows. You will simulate and implement your design. Your design will be a pipelined processor containing a five cycle pipeline and capable of resolving data dependencies in hardware. As a final point, you are required to run an architectural verification program (AVP). This program will exercise all of the architected instructions and verify that your processor operates correctly. If your processor can pass the test - you have succeeded. Pre-lab: You must show up to each of the lab sessions with your pre-lab completed. Otherwise, you will not be allowed to proceed with the lab. You have four weeks to complete this project. However, beware that if you do not start working immediately you will loose your precious time and ultimately fail. For pre-lab, do the complete paper design for the problem given below: Lab 7. Complete a drawing of a block level organization of your computer. Identify all the registers that you need, multiplexers, major logic units, data paths and buses and all the control signals: a. List them. b. Provide the timing diagram for each of the instructions and show which control signals are activated and when for each of the instructions. c. Provide the state-transition diagram and show clearly how will each instruction follow those states and in which phases. Lab 8. Explain how are you going to implement pipelining and how are you going to resolve the data-dependencies. Draw a detailed diagram explaining the function and the structure of each component you are using. a. Show all the possible conflicts between instructions (list them) b. Show your solution for each one of the conflicts listed. c. Show a detailed diagram of your data-path Lab 9. Show the detailed diagram of your Control Unit. a. Assign op-codes for your instructions. Explain advantage of your op-codes over the ones provided to you in this lab. How do they affect your control ?EEC 180B: Prof. V.G. Oklobdzija MICRO-PROCESSOR DESIGN: MISP 2 Lab 10. Show your AVP and explain your verification strategy. I. Minimal Instruction Set Processor (MISP) Design: MISP Architecture Document General: MISP architecture is given by the Instruction Set Architecture (ISA) and the registers that are visible to the programmer. MISP is an 16-bit processor which data-path is 16-bits long and all of the instructions are register-to-register instructions 16-bit long. The architecturally visible register file contains 8 16-bit registers. Register R0 is wired to the value 0. This allows for fast comparisons and branches. The data is treated as two's complement format representation for all the arithmetic operations. Arithmetic operation that involves Immediate field treats this 6-bit filed as 2's complement number. For logical operation the data is treated as 16-bits data. Instruction Formats: There are five instruction formats used in MISP. Opcode field is 5-bits long allowing for inclusion of 32 instructions in the ISA of MISP processor. Load / Store: 0 4 7 10 15 Load and Store instruction uses Base + Displacement addressing mode. The destination register is specified by the field designated as R1. The base register is specified as R2 and this can be any register in the register file. Displacement field is carried with the instruction and it is 5-bits long allowing for a displacement of 31 entries from the beginning of a 32-entry page. There are no flags set by this instructions and it is assumed that the data is always available. Load Immediate: 0 4 7 15 Load Immediate instructions loads the value specified in the 8-bit immediate field into the designated register. The value is treated as an unsigned integer. There are no flags set by this instruction. LD / ST R1 R2 D LDI R1 ImmediateEEC 180B: Prof. V.G. Oklobdzija MICRO-PROCESSOR DESIGN: MISP 3 Arithmetic / Logic: 0 4 7 10 13 15 0 4 7 10 15 Arithmetic and logic instructions are of a RISC format, explicitly specifying the destination register R1, and two of the operand registers R2 and R3. The register field is 3-bits long allowing for each of the 8 registers to be addressed. Another format used for Arithmetic operations only is Immediate format where a short 5-bit constant is carried in the instruction. Immediate field is treated as a 2's complement number. Therefore, the maximal number that can be directly coded into the instruction is 15 and the minimal -16. Both Arithmetic instructions set the three condition bits in the condition code register: N-negative, Z-zero result, Ov - overflow. Logic instructions are using the three register format only. They do not set condition bits in the condition code register. Branch: 0 4 5 15 Branch instruction tests the condition of one of the four condition bits of the condition register: N negative C carry out (this is C16 out of the ALU) V overflow bit (this is a logical XOR of C16 and C15) Z result equal to zero OP R1 R2 R3 OP R1 R2 Imm BR OffsetEEC 180B: Prof. V.G. Oklobdzija MICRO-PROCESSOR DESIGN: MISP 4 The condition bits are always set by the last instruction that modifies the condition codes. If any one of the specified conditions is true the processor branches to the address specified as: OffsetIARIAR+← Where IAR designates Instruction Address Register. The Offset field is 11-bits long which means that the processor can branch ahead for 1023, -1024 instructions from the current one. Therefore the branch is relative. Input / Output: 0 4 7 15 Input and Output instruction transfer the data from IN and OUT peripheral register correspondingly. Input instruction (IN) transfer the content of the IN register to the general purpose register specified as