IOBsIOB OverviewStorage Element FunctionsDouble-Data-Rate TransmissionPull-Up and Pull-Down ResistorsKeeper CircuitESD ProtectionSlew Rate Control and Drive StrengthBoundary-Scan CapabilitySelectIO Signal StandardsDigitally Controlled Impedance (DCI)The Organization of IOBs into BanksSpartan-3 CompatibilityRules Concerning BanksExceptions to Banks Supporting I/O StandardsSupply Voltages for the IOBsThe I/Os During Power-On, Configuration, and User ModeCLB OverviewElements Within a SliceMain Logic PathsFunction GeneratorBlock RAM OverviewArrangement of RAM Blocks on DieThe Internal Structure of the Block RAMBlock RAM Port Signal DefinitionsPort Aspect RatiosBlock RAM Data OperationsDedicated MultipliersDigital Clock Manager (DCM)Delay-Locked Loop (DLL)Digital Frequency Synthesizer (DFS)Phase Shifter (PS)The Status Logic ComponentGlobal Clock NetworkInterconnectConfigurationThe Standard Configuration Interface3.3V-Tolerant Configuration InterfaceConfiguration ModesAdditional Configuration DetailsPowering Spartan-3 FPGAsVoltage RegulatorsPower Distribution System (PDS) Design and Bypass/Decoupling CapacitorsPower-On BehaviorConfiguration Data Retention, Brown-OutRevision HistoryThe Spartan-3 Family Data SheetDS099-2 (v1.4) August 19, 2005 www.xilinx.com 1Product Specification© 2004, 2005 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.IOBsIOB OverviewThe Input/Output Block (IOB) provides a programmable,bidirectional interface between an I/O pin and the FPGA’sinternal logic. A simplified diagram of the IOB’s internal structure appearsin Figure 1. There are three main signal paths within theIOB: the output path, input path, and 3-state path. Eachpath has its own pair of storage elements that can act aseither registers or latches. For more information, see theStorage Element Functions section. The three main sig-nal paths are as follows:• The input path carries data from the pad, which isbonded to a package pin, through an optionalprogrammable delay element directly to the I line.There are alternate routes through a pair of storageelements to the IQ1 and IQ2 lines. The IOB outputs I,IQ1, and IQ2 all lead to the FPGA’s internal logic. Thedelay element can be set to ensure a hold time of zero.• The output path, starting with the O1 and O2 lines,carries data from the FPGA’s internal logic through amultiplexer and then a three-state driver to the IOBpad. In addition to this direct path, the multiplexerprovides the option to insert a pair of storage elements. • The 3-state path determines when the output driver ishigh impedance. The T1 and T2 lines carry data fromthe FPGA’s internal logic through a multiplexer to theoutput driver. In addition to this direct path, themultiplexer provides the option to insert a pair ofstorage elements. When the T1 or T2 lines areasserted High, the output driver is high-impedance(floating, Hi-Z). The output driver is active-Lowenabled.• All signal paths entering the IOB, including thoseassociated with the storage elements, have an inverteroption. Any inverter placed on these paths isautomatically absorbed into the IOB.Storage Element FunctionsThere are three pairs of storage elements in each IOB, onepair for each of the three paths. It is possible to configureeach of these storage elements as an edge-triggeredD-type flip-flop (FD) or a level-sensitive latch (LD).The storage-element-pair on either the Output path or theThree-State path can be used together with a special multi-plexer to produce Double-Data-Rate (DDR) transmission.This is accomplished by taking data synchronized to theclock signal’s rising edge and converting them to bits syn-chronized on both the rising and the falling edge. The com-bination of two registers and a multiplexer is referred to as aDouble-Data-Rate D-type flip-flop (FDDR).See Double-Data-Rate Transmission, page 3 for moreinformation.The signal paths associated with the storage element aredescribed in Table 1.042Spartan-3 FPGA Family:Functional DescriptionDS099-2 (v1.4) August 19, 200500Product SpecificationRTable 1 : Storage Element Signal DescriptionStorage Element SignalDescription FunctionD Data input Data at this input is stored on the active edge of CK enabled by CE. For latch operation when the input is enabled, data passes directly to the output Q. Q Data output The data on this output reflects the state of the storage element. For operation as a latch in transparent mode, Q will mirror the data at D.CK Clock input A signal’s active edge on this input with CE asserted, loads data into the storage element. CE Clock Enable input When asserted, this input enables CK. If not connected, CE defaults to the asserted state. SR Set/Reset Forces storage element into the state specified by the SRHIGH/SRLOW attributes. The SYNC/ASYNC attribute setting determines if the SR input is synchronized to the clock or not.REV Reverse Used together with SR. Forces storage element into the state opposite from what SR does.Spartan-3 FPGA Family: Functional Description2 www.xilinx.com DS099-2 (v1.4) August 19, 2005Product Specification42RFigure 1: Simplified IOB DiagramDCECKTFF1Three-state PathTT1TCET2TFF2QSRDDRMUXREVDCECKQSR REVDCECKOFF1Output PathO1OCEO2OFF2QSRDDRMUXKeeperLatchVCCOVREFPinI/O Pin fromAdjacentIOBDS099-2_01_082104I/OPinProgram-mableOutputDriverDCIESDPull-UpPull-DownESDREVDCECKQSR REVOTCLK1OTCLK2DCECKIFF1Input PathIICEIFF2QSRFixedDelayLVCMOS, LVTTL, PCISingle-ended Standardsusing VREFDifferential StandardsREVDCECKQSR REVICLK1ICLK2SRREVNote: All IOB signals communicating with the FPGA's internal logic have the option of inverting polarity.IQ1IQ2Spartan-3 FPGA Family: Functional DescriptionDS099-2 (v1.4) August 19, 2005 www.xilinx.com 3Product SpecificationRAccording to Figure 1, the clock line OTCLK1 connects theCK inputs of the upper registers on the output andthree-state paths. Similarly, OTCLK2 connects the CKinputs for the lower registers on the output and three-statepaths. The upper and lower registers on the input path haveindependent clock lines: ICLK1 and ICLK2.The enable line OCE connects the CE inputs of the upperand lower registers on the output path. Similarly, TCE con-nects the CE inputs for the register pair on the three-statepath and ICE