University of California, DavisDepartment of Electrical and Computer EngineeringEEC180B DIGITAL SYSTEMS II Spring 1999Lab 6: Register File Design in VHDLObjective: In this lab you will design a small register file in VHDL and verify it byfunctional simulation. The register file will be a component in the final processor lab.Pre-lab: Write a complete, syntactically correct VHDL process that implements a 4:1bus multiplexer using a case statement. The multiplexer will direct one of four 8-bitbuses to the 8-bit output, under the control of the two-bit select input. Show thedeclaration of all signals used in your process.Note: this lab and pre-lab are to be done individually. That is, you may not work withanyone else or use anyone else’s work.Problem SpecificationDesign a register file consisting of four eight-bit registers, R0 - R3. The external interfaceof the register file is shown in Figure 1.AB888Figure 1 : External Interface of the Register FileRegister File (4x8)A_addB_addWB_addWBclkwr_en R0R1R2R3222There are two read buses, A and B, and one write bus, WB. There are also three two-bitaddress buses, A_add, B_add, and WB_add. Each of these address buses is used tospecify one of the four registers for either reading or writing. The write operation takesplace on the rising edge of the clk signal when the wr_en signal is logic 1. The readoperation, however, is not clocked - it is combinational. Thus, the value on the A busshould always be the contents of the register specified by the A_add bus. Similarly, thevalue on the B bus should always be the contents of the register specified by the B_addbus. So, with this register file, you can write into a register and read two registerssimultaneously. It is also possible to read a single register on both of the read busessimultaneously. Your VHDL model must not infer tri-state buffers. Your code mustgenerate combinational logic to multiplex signals rather than tri-state buffers.Lab GuidelinesThe entity of the VHDL model should be as follows:entity regfile isport (clk, wr_en : in std_logic; A_add, B_add, WB_add : in std_logic_vector(1 downto 0); WB : in std_logic_vector(7 downto 0); A, B : out std_logic_vector(7 downto 0));end regfile;Note that you do not need a reset signal in your design. The registers in the register filewill be undefined until data is written into them. (In the final processor design, you willuse a special reset buffer, STARTBUF, to drive the GSR signal in the Xilinx FPGA so thatyou can reset all the flip-flops in your design by pressing the reset switch.)The registers in the register file can be declared using an array. This is not required, but itis a convenient way to reference the registers.Lab Requirements1. Complete the pre-lab assignment, working entirely alone, before your first lab period.2. Write a synthesizable VHDL model of the register file. Use a separate process for theclocked logic that implements the write operation. Use one or more processes orconcurrent statements for the combinational logic that implements the read operation.3. Write a test bench to verify the operation of the circuit. Verify that you can correctlyread from and write to each register in the register file. Also verify that the wr_ensignal works correctly. Demonstrate your simulation to your TA for verification.4. Synthesize the sequential machine for the Xilinx library. Make sure you are using the.synopsys_dc.setup file for the Xilinx library. Print the gate-level schematic from theSynopsys Design Analyzer. Since you will not be downloading this design to a Xilinxboard, you do not need to use an attribute file.5. Examine the synthesis log file and make sure you did not infer latches in your design.The log file should report how many flip-flops were inferred.Lab ReportSubmit the following items in your lab report: (Due in your first lab period of thefollowing week - i.e. one week after the start of the lab.)q All VHDL source code.q Test bench source code.q Simulation waveforms from your functional simulationq Gate-level schematic of your register file printed from the Design Analyzer.q Signed TA verification for the functional simulation.q From the various Xilinx report files, record the number of flip-flops and CLBs usedin your design. Print the summary of FPGA resource usage from the appropriatereport file and indicate which report file you used.q Answer the following question:1. Compare the expected synthesis results in using the following three VHDLconstructs to multiplex 4 or more inputs to an output: Case statement If then elsif statement Conditional signal assignmentWhich construct would you expect to generate the fastest multiplexer? Why? Iftime permits, you could test your answer by coding multiplexers with each of theconstructs and analyzing and elaborating the code with the Synopsys DesignAnalyzer, although this is not