UCD EEC 180B - Lab 2- Register File Design (2 pages)

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Lab 2- Register File Design



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Lab 2- Register File Design

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Pages:
2
School:
University of California, Davis
Course:
Eec 180b - Projects in Com Networks

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UNIVERSITY OF CALIFORNIA DAVIS Department of Electrical and Computer Engineering EEC180B DIGITAL SYSTEMS II Fall 1999 Lab 2 Register File Design Objective In this lab you will design and simulate a Register File that will be used later in the design of a pipelined processor I Register File Specifications A Register File is an integral part of a microprocessor Registers are used to store operands for ALU operations addresses for branch instructions and data in the form of intermediate values during a computation The number of registers and the width of each register characterize a Register File An MxN Register File has M registers each of which is N bits wide Typically a Register File supports two operations namely read and write A read operation involves placing the data value within a given register onto an output bus while a write operation involves storing a given value into a specified register In this lab you will design and simulate a Register File consisting of eight 16 bit registers R0 R7 Register R0 should be hardwired to zero That is reading from R0 should always give the value 0 and writing to R0 should have no effect The external interface of the Register File is shown in Figure 1 There are two read buses A and B and one write bus WB There are also three three bit address buses A add B add and WB add Each of these address buses is used to specify one of the 8 registers for either reading or writing The write operation takes place on the rising edge of the clk signal when the wr en signal is logic 1 The read operation however is not clocked it is combinational Thus the contents of the register specified by the A add bus should always be on the A bus Similarly the contents of the register specified by the B add bus should always be on the B bus So with this Register File you can write into a register and read two registers simultaneously It is also possible to read a single register on both of the read buses simultaneously 16 3 3 3 WB add WB clk A add 8x16



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