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IntroductionPin DescriptionsPin TypesPin DefinitionsDetailed, Functional Pin DescriptionsI/O Type: Unrestricted, General-purpose I/O PinsDUAL Type: Dual-Purpose Configuration and I/O PinsDCI: User I/O or Digitally Controlled Impedance Resistor Reference InputGCLK: Global Clock Buffer Inputs or General-Purpose I/O PinsCONFIG: Dedicated Configuration PinsJTAG: Dedicated JTAG Port PinsVREF: User I/O or Input Buffer Reference Voltage for Special Interface StandardsN.C. Type: Unconnected Package PinsVCCO Type: Output Voltage Supply for I/O BankVCCINT Type: Voltage Supply for Internal Core LogicVCCAUX Type: Voltage Supply for Auxiliary LogicGND Type: GroundPin Behavior During ConfigurationBitstream OptionsSetting Bitstream Generator OptionsPackage OverviewSelecting the Right Package OptionMechanical DrawingsPower, Ground, and I/O by PackageVQ100: 100-lead Very-thin Quad Flat PackagePinout TableUser I/Os by BankVQ100 FootprintCP132: 132-ball Chip-Scale PackagePinout TableUser I/Os by BankCP132 FootprintTQ144: 144-lead Thin Quad Flat PackagePinout TableUser I/Os by BankTQ144 FootprintPQ208: 208-lead Plastic Quad Flat PackPinout TableUser I/Os by BankPQ208 FootprintFT256: 256-lead Fine-pitch Thin Ball Grid ArrayPinout TableUser I/Os by BankFT256 FootprintFG320: 320-lead Fine-pitch Ball Grid ArrayPinout TableUser I/Os by BankFG320 FootprintFG456: 456-lead Fine-pitch Ball Grid ArrayPinout TableUser I/Os by BankFG456 FootprintFG676: 676-lead Fine-pitch Ball Grid ArrayPinout TableUser I/Os by BankFG676 FootprintFG900: 900-lead Fine-pitch Ball Grid ArrayPinout TableUser I/Os by BankFG900 FootprintFG1156: 1156-lead Fine-pitch Ball Grid ArrayPinout TableUser I/Os by BankFG1156 FootprintRevision HistoryThe Spartan-3 Family Data SheetDS099-4 (v1.7) August 19, 2005 www.xilinx.com 1Product Specification© 2004, 2005 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.IntroductionThis data sheet module describes the various pins on aSpartan™-3 FPGA and how they connect to the supportedcomponent packages.•The Pin Types section categorizes all of the FPGApins by their function type.•The Pin Definitions section provides a top-leveldescription for each pin on the device.•The Detailed, Functional Pin Descriptions sectionoffers significantly more detail about each pin,especially for the dual- or special-function pins usedduring device configuration.• Some pins have associated behavior that is controlledby settings in the configuration bitstream. Theseoptions are described in the Bitstream Optionssection.•The Package Overview section describes the variouspackaging options available for Spartan-3 FPGAs.Detailed pin list tables and footprint diagrams areprovided for each package solution.Pin DescriptionsPin TypesA majority of the pins on a Spartan-3 FPGA are gen-eral-purpose, user-defined I/O pins. There are, however, upto 12 different functional types of pins on Spartan-3 pack-ages, as outlined in Ta ble 1 . In the package footprint draw-ings that follow, the individual pins are color-codedaccording to pin type as in the table.0109Spartan-3 FPGA Family: Pinout DescriptionsDS099-4 (v1.7) August 19, 200500Product SpecificationRTabl e 1: Types of Pins on Spartan-3 FPGAsType/ Color CodeDescription Pin Name(s) in TypeI/O Unrestricted, general-purpose user-I/O pin. Most pins can be paired together to form differential I/Os.IO, IO_Lxxy_#DUAL Dual-purpose pin used in some configuration modes during the configuration process and then usually available as a user I/O after configuration. If the pin is not used during configuration, this pin behaves as an I/O-type pin. There are 12 dual-purpose configuration pins on every package.IO_Lxxy_#/DIN/D0, IO_Lxxy_#/D1, IO_Lxxy_#/D2, IO_Lxxy_#/D3, IO_Lxxy_#/D4, IO_Lxxy_#/D5, IO_Lxxy_#/D6, IO_Lxxy_#/D7, IO_Lxxy_#/CS_B, IO_Lxxy_#/RDWR_B, IO_Lxxy_#/BUSY/DOUT, IO_Lxxy_#/INIT_BCONFIG Dedicated configuration pin. Not available as a user-I/O pin. Every package has seven dedicated configuration pins. These pins are powered by VCCAUX.CCLK, DONE, M2, M1, M0, PROG_B, HSWAP_ENJTAG Dedicated JTAG pin. Not available as a user-I/O pin. Every package has four dedicated JTAG pins. These pins are powered by VCCAUX.TDI, TMS, TCK, TDODCI Dual-purpose pin that is either a user-I/O pin or used to calibrate output buffer impedance for a specific bank using Digital Controlled Impedance (DCI). There are two DCI pins per I/O bank.IO/VRN_#IO_Lxxy_#/VRN_#IO/VRP_#IO_Lxxy_#/VRP_#VREF Dual-purpose pin that is either a user-I/O pin or, along with all other VREF pins in the same bank, provides a reference voltage input for certain I/O standards. If used for a reference voltage within a bank, all VREF pins within the bank must be connected.IO/VREF_#IO_Lxxy_#/VREF_#Spartan-3 FPGA Family: Pinout Descriptions2 www.xilinx.com DS099-4 (v1.7) August 19, 2005Product SpecificationRI/Os with Lxxy_# are part of a differential output pair. ‘L’ indi-cates differential output capability. The “xx” field is atwo-digit integer, unique to each bank that identifies a differ-ential pin-pair. The ‘y’ field is either ‘P’ for the true signal or‘N’ for the inverted signal in the differential pair. The ‘#’ fieldis the I/O bank number.Pin DefinitionsTab l e 2 provides a brief description of each pin listed in theSpartan-3 pinout tables and package footprint diagrams.Pins are categorized by their pin type, as listed in Ta bl e 1.See Detailed, Functional Pin Descriptions for more infor-mation.GND Dedicated ground pin. The number of GND pins depends on the package used. All must be connected.GNDVCCAUX Dedicated auxiliary power supply pin. The number of VCCAUX pins depends on the package used. All must be connected to +2.5V.VCCAUXVCCINT Dedicated internal core logic power supply pin. The number of VCCINT pins depends on the package used. All must be connected to +1.2V.VCCINTVCCO Dedicated I/O bank, output buffer power supply pin. Along with other VCCO pins in the same bank, this pin supplies power to the output buffers within the I/O bank and sets the input threshold voltage for some I/O standards.VCCO_#CP132 and TQ144 Packages Only:VCCO_LEFT, VCCO_TOP, VCCO_RIGHT, VCCO_BOTTOMGCLK Dual-purpose pin that is either a user-I/O pin or an input to a specific


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UCD EEC 180B - LECTURE NOTES

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