EEC180B Lab 3 - Synopsys TutorialUniversity of California, DavisDepartment of Electrical and Computer EngineeringObjective: The purpose of this tutorial is to introduce the Synopsys simulation andsynthesis tools. A simple VHDL description of an up/down binary counter will befunctionally simulated. The design will then be synthesized into generic gates using anexample "class" library or into a Xilinx field programmable gate array (FPGA). Afterusing Xilinx software to process the Synopsys output file, the design can be downloadedto a Xilinx FPGA and tested. An exercise is provided at the end of the tutorial to testyour understanding of the high-level design process.I. Setting up the environment First set up your environment for the Synopsys and Xilinx tools. To do this, run the setupscript by typing the following command:setup synopsys9802If your environment isn’t set up for the Xilinx tools, run the setup script for Xilinx:setup xilinxThese setup scripts just need to be run once. Open a new window or log out and logback in to get the new environment. After getting a new window, type the followingcommands to verify that your configuration:echo $XILINXecho $SYNOPSYSThese commands should display the UNIX paths to the Xilinx and Synopsys rootdirectories, respectively.Now create a new directory for the tutorial exercises and copy the tutorial files into it.Once you have changed directory to your new directory, use the following commandswhere the final period is the UNIX designation for your current directory:cp /afs/ece/classes/eec180b/xtutorial/.sy* .cp /afs/ece/classes/eec180b/xtutorial/*.* .The .synopsys_vss.setup and the .synopsys_dc.setup files specify the default workingdirectory as ./WORK, which means that you must create a WORK subdirectory underyour current directory.mkdir WORKII. On-line documentation The Synopsys on-line documentation is available by typing the command:soldThe Simulation Tools and the Synthesis Tools collections have a number of usefulreferences. Each collection also has a set of documents, which are formatted for printingsuch as the Simulation Documents for Printing or the Synthesis Documents for Printing.The VSS Quick Start tutorial, which is in the Simulation Tools collection, is a usefulguide to the Synopsys simulator. (It is available as a print-formatted version as well as aversion for on-line use.)The Xilinx documentation is also available on-line using the command:dtext &The Synopsys (XSI) Interface/Tutorial Guide is a useful reference for this course.III. Functional Simulation To simulate the updown counter design, you must first compile, or analyze, the VHDLsource files to generate files which the VHDL Simulator can use. The updown designconsists of two files, my_pkg.vhd and updown.vhd, which must both be analyzed usingthe commands shown below. Since my_pkg is referenced in the updown design file,my_pkg.vhd should be analyzed first.vhdlan -i my_pkg.vhdvhdlan -i updown.vhdYou will use a testbench VHDL file, tb.vhd, to provide part of the simulation inputs.You must analyze this file also so that it can be simulated. However, this file will not besynthesized.vhdlan -i tb.vhdNow you are ready to simulate the counter. The Synopsys VHDL Debugger, vhdldbx,can be used for interactive simulation sessions. Run the following command:vhdldbx &The design, which we want to simulate, is the configuration of the testbench program.Select TB_CFG in the design window and click on the OK box to bring up the VHDLDebugger.To trace all the signals in the top-level design file (i.e. the testbench), type the followingat the Command prompt (#):tr *’signalYou should also trace the count signal, which is declared in the updown design. You canchange the "working region" by typing:cd uutIn the VHDL Debugger source code region, double-click on the signal name count andclick on the Trace button. Alternatively, you could type tr count at the Commandprompt. A third method would be to type tr uut/count from the original workingregion.The trace commands should bring up a Waveform Viewer window. Since our stimulus ispartially coded into the testbench file, we can simply run for some amount of time andobserve the signal waveforms.run 200The count value should be cleared to 0 since the reset signal was low for a clock cycle.Notice that the enable and up_dn signals are undefined since the testbench program doesnot initialize these signals. To assign a logical 0 to these signals, type the following atthe Command prompt:as ’0’ enable up_dnrun 200The enable and up_dn signals should be low in the Waveform Viewer. Since the enablesignal is active-high, the count remains at 0. To enable counting, use the followingcommands:as ’1’ enablerun 600You can continue entering commands at the Command prompt and testing the counter asdesired. The reset signal can also be tested using the assign command:as ’0’ resetrun 200as ’1’ resetAnother way to enter simulation commands is through a simulation command file. Closethe Waveform Viewer window by selecting File -> Exit. Then Choose Execute ->Restart from the Vhdldbx menu bar in order to restart your simulation. Delete theArguments field in the dialog box and again select the TB_CFG design with theDEFAULT library. Run a simulation by typing the following command at the Commandprompt:include sim.scriptVerify the simulation and make sure you understand the sim.script commands. Thesim.script file is an ASCII text file so you can use vi or another editor to view or modifythe script. Modify the simulation script to fully test the counter.Occasionally, the Synopsys Waveform Viewer will not display the waveforms eventhough the correct simulation commands have been given. Check your directory for anywaveform files (the final suffix of the file will be .ow). You can use File -> Open fromthe Waveform Viewer pull-down menus to view the waveform stored in the file. Thisfile can also be safely deleted when you are done viewing it.IV. Synthesis Part A - Class library In this section, you will synthesize the design to generic gates using an example "class"library. You must set the .synopsys_dc.setup file to point to the correct target libraries.There are two example .synopsys_dc.setup files included in the tutorial files. To targetthe class library, typecopy .synopsys_dc.setup.class .synopsys_dc.setupThe Synopsys tools which are used for synthesis are the Design Compiler or the DesignAnalyzer. In order to