UNIVERSITY OF CALIFORNIA, DAVISDepartment of Electrical and Computer EngineeringEEC180A DIGITAL SYSTEMS IADVANCED ALTERA MAX + PLUS II TUTORIALOVERVIEWThis tutorial illustrates several advanced topics which were not covered in Lab 1. These topicsinclude creating symbols for use in a hierarchical design, using Altera parameterized modules,such as ROM, and initializing ROM contents.USING PARAMETERIZED MODULESAltera's Library of Parameterized Modules (LPM) contains many high-level components whichcan be configured to meet specific design goals. You will probably find the LPM componentsvery convenient and easy to use.In this tutorial, you will design a circuit will computes the Fibonacci sequence using an adderand registers. (The Fibonacci sequence is 0, 1, 1, 2, 3, 5, 8, ...) The data path will be 8-bits wideso that the circuit can be easily tested using the Altera Education Board.• Recall that there are many ways to execute commands in the Altera environment. You canuse the pull-down menus, a pop-up menu which is available when you click the right-mousebutton, keyboard shortcut commands, or the toolbar buttons. To see the definition of atoolbar button, move the mouse so that the cursor is on top of the button. The button'sfunction will be described at the lower-left corner of your window.• Open a new schematic and enter the symbol lpm_add_sub from the mega_lpm library. Adialog box should come up to allow you to configure the parameters and ports. Click on eachparameter from the list and use the pull-down arrow in the dialog box to select the desiredvalue for the parameter. Enter the following values for the parameters:LPM_DIRECTION = "ADD"LPM_REPRESENTATION = "UNSIGNED"LPM_WIDTH = 8Any other parameters, such as LPM_PIPELINE or ONE_INPUT_IS_CONSTANT, shouldbe left unassigned. For an explanation on how the lpm_add_sub component works and howeach of the parameters can be used, select the Help on LPM_ADD_SUB button in the dialogbox.Configure the ports so that cin, cout, dataa[], datab[] and result[] are Used and all otherports are Unused. (Select each port name from the list and click on the Used or Unusedbutton.) When you have configured all ports and parameters, press the OK button.If you need to change any parameters or port declarations after you have closed the dialogbox, click on the lpm_add_sub component on your schematic and select EditPorts/Parameters... (Symbol menu). This will re-open the dialog box so that you can makecorrections. Another way to re-open the dialog box is to double-click the left-mouse button(LMB) on the parameters box.The adder will be used to add the last two numbers in the sequence to produce the next number.We will also need two 8-bit registers in order to store the last two numbers in the sequence. Wecould use a standard D flip-flop and let the Altera software create a "primitive array". However,the standard D flip-flop only has an asynchronous reset and in our design we would like tosynchronously clear the registers when a carry-out is generated by the adder. We can use anotherLPM component to design a D flip-flop with both asynchronous and synchronous clear inputs.• Enter the symbol lpm_dff from the mega_lpm library. Set the parameters such thatLPM_WIDTH = 8 and the other parameters are unassigned. Configure ports aclr, clock,data[], q[] and sclr as Used and all other ports as Unused.• Make a copy of the lpm_dff that you just configured and place the components as shown inFigure 1. Also, add the components not, dff, input and output and complete the schematicas shown in Figure 1. Note that buses are shown with a thick line and are labeled asNAME[MSB..LSB].• Label the output bus with your first name. i.e. FRANK[7..0]. Also, label the output of thelpm_add_sub component with your initials followed by _SUM[7..0]. Note that wires whichhave the same name on the same level of hierarchy areconnected. Remember to keep thewire labels close to wires which they label. Otherwise, the Altera Compiler may not interpretthe text as a valid net label.• Save & Check your file to make sure that there are no errors. The Check command opens upthe Compiler tool and performs the first part of a circuit compilation. With the Compiler toolstill open, select the following options from the Processing menu: Functional SNFExtractor and Preserve All Node Name Synonynms. (You will have to turn off theTiming SNF Extractor before you can select the Functional SNF Extractor.) Once theoptions are selected, click on the Start button to compile your circuit. You must fix anycompile errors before proceeding to the next step.• Open the Waveform Editor and select the Nodes to watch during simulation. You can useEnter Nodes from SNF... (Node menu) to select nodes such as RESET, CLK and the outputsignal with your name. Some other nodes are difficult to find in the SNF list. Instead, youcan select Insert Node (Node menu) and type the name of a node. Try this for enteringnodes A[7..0], CIN, COUT and the output of the lpm_add_sub which has your initials in thename.• Set the Grid Size(Options menu) to 20 ns.• Select the CLK node with the left-mouse button so that it is highlighted. Then selectOverwrite > Clock from the Edit pull-down menu. Specify a clock period of 40 ns.• Assert the RESET node high for the first clock cycle. (Note that the RESET is active-high inthis design.) Run a functional simulation and compare your results with Figure 2.CREATING A SYMBOLYou will now create a symbol for the circuit you have just designed so that it can be used as acomponent in a more complex design.• Open the graphic design file (.gdf) for your circuit. Select Create Default Symbol (Filemenu). This will create a symbol file with the same name as your design and the .symextension.CREATING A HIERARCHICAL DESIGNYou will now design a top-level schematic which uses the component you just created.• Close any open windows such as the Graphics Editor, Simulator, Waveform Editor, etc.Create a new schematic file (.gdf) for your top-level design. Name the file and save it in yourworking directory. Change the project to this new name.• Place an instance of your component in your top-level schematic. Your symbol should haveRESET and CLK input ports and an output port named after you.USING ROMIn this design, we will use ROM to implement a combinational logic circuit which converts a 4-bit hex number to the corresponding 7-segment display driver