CSE 291 IHigh Performance Interconnect and Packaging Winter 2008 University of California San Diego Course Information Instructor CK Cheng ckcheng 291 ucsd edu 858 534 6184 Schedule Lectures 2 00 3 20PM TTH SSB 106 Textbooks H High Speed Signal Propagation Advanced Black Magic Howard Johnson and Martin Graham D Digital Systems Engineering William J Dally John W Poulton Content 1 Structure of Interconnect and Packaging D2 2 Electrical and Physical Scaling D1 H1 3 Transmission Line Model D3 H2 4 Interconnect Signaling D7 D8 H3 H5 H6 5 Transmitters and Receivers D4 D11 6 Timing Interface D10 7 Timing Components D12 8 Noises D6 9 Power Distribution D5 10 Clock Distribution D9 H12 11 Physical Interface 12 Heat Dissipation 13 Modeling and Simulation Interconnect and Packaging Cost Materials pins layers wire densities Heat sinks Performance Bandwidth Latency Power Distribution RLC and Voltage Regulator Consumption Thermal Dissipation System Examples Blue Gene L 2005 25KW Rack 64Racksx 2Midplanesx 16Node cardsx 8Compute cardsx 2PUs 64x32x32 Torus 1 4Gb s differential link 700MHz clock z900 2002 1 3KW MCM 20 PUs 918MHz 2 10x3cross bar 16K nets 459MHz Source synchronous and elastic receiver System Examples z9 2007 CP 15 8x11 8mm2 2962pins 603sigs MCM 12KW 95x95mm2 102 layers 6mil thick 5184pins 2970sigs 16 dual core processors at 1 72GHz 128GB mem per MCM On MCM interconnect 1 72Gbps clamping Off MCM interconnect 860Mbps predistortion clamping Source synchronous and elastic receiver Processor Packaging On Chip Interconnect Silicon to Package Interface Density of pins On Package Interconnect Pin breakaway Via density Wire density Power Distribution
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