Understanding Network Processors By Niraj Shah niraj eecs berkeley edu VERSION 1 0 4 SEPTEMBER 2001 Understanding Network Processors Table of Contents 0 1 Intended Audience 1 Introduction 2 1 1 What is a Network Processor 5 1 2 A Brief History 5 2 A Profile of Network Applications 7 2 1 Network applications 7 2 2 Kernels 22 2 3 Summary 23 3 Network Processors 27 3 1 Agere PayloadPlus 27 3 2 Alchemy Au1000 30 3 3 Applied Micro Circuits formerly MMC Networks nP7xxx 31 3 4 Bay Microsystems 32 3 5 BRECIS Communications MSP5000 33 3 6 Broadcom formerly SiByte Mercurian SB 1250 34 3 7 Cisco PXF Toaster 2 35 3 8 ClearSpeed formerly PixelFusion 36 3 9 Clearwater Networks formerly XStream Logic Devices CNP810SP 37 3 10 Cognigine 39 3 11 Conexant formerly Maker MXT4400 Traffic Stream Processor 40 3 12 EZchip NP 1 41 3 13 IBM PowerNP 42 3 14 Intel formerly Level One IXP1200 44 3 15 Lexra NetVortex NVP 46 3 16 Motorola formerly C Port C 5 DCP 48 3 17 PMC Sierra formerly Quantum Effect Devices 50 3 18 Vitesse formerly SiTera PRISM IQ2000 50 3 19 Xelerated Packet Devices X40 T40 51 3 20 Summary 53 4 Analysis 55 4 1 Market Segmentation 55 4 2 Architecture 56 4 3 Programmability 63 4 4 Summary 65 5 Looking Forward 67 5 1 Applications 67 5 2 Architecture 67 5 3 Mapping Applications onto Architectures 69 6 Conclusions 71 7 Web Sites 72 8 Acronym Dictionary 74 9 References 75 Appendix 79 A Detailed Network Processor Summary 79 B Applications Architecture Mapping Table 87 i Understanding Network Processors List of Figures Figure 1 Space of System Implementations 3 Figure 2 Comparison of System Implementations 4 Figure 3 The Solution Space of Network Processing 5 Figure 4 OSI Protocol Stack 7 Figure 5 ATM cell header 8 Figure 6 The protocol stack for IP over ATM 9 Figure 7 Internet Protocol IP Header Format 10 Figure 8 IPv6 Packet Header Format 13 Figure 9 Type 0 Routing Extension 14 Figure 10 Difference between Transport and Tunnel mode 14 Figure 11 AH Header Format 15 Figure 12 ESP Header Format 16 Figure 13 TCP header and optional data 17 Figure 14 Wireless TCP IP Gateway 18 Figure 15 Logical view of a DiffServ node 21 Figure 16 Agere PayloadPlus System 28 Figure 17 FPP Block Diagram 24 29 Figure 18 Architecture of the Agere Routing Switch Processor 26 30 Figure 19 Alchemy s System Architecture 29 31 Figure 20 Applied Micro Circuits EPIF 200 Network Processor 30 32 Figure 21 BRECIS Communications MSP5000 34 34 Figure 22 Broadcom s Mercurian Architecture 37 35 Figure 23 Example use of Cisco s PXF NP 39 36 Figure 24 Macro Architecture of Clearwater Networks CNP810SP Network Processor 38 Figure 25 Cognigine s RCU Architecture 40 Figure 26 EZChip s NP 1 Architecture 45 41 Figure 27 IBM s Network Processor 50 43 Figure 28 Embedded Processor Complex Architecture 50 43 Figure 29 Ingress and Egress Frame Flow 50 44 Figure 30 Intel s IXP1200 Architecture 45 Figure 31 An Example Use of Lexra s NetVortex System Architecture 56 47 Figure 32 Motorola C 5 DCP Macro architecture 60 49 Figure 33 Vitesse s PRISM IQ2000 Architecture 64 51 Figure 34 Macro architecture of the X40 52 Figure 35 Example use of Xelerated s X40 Packet Processor 53 Figure 36 Varying Solutions of Network Processors 54 Figure 37 Timeline of Network Processor Releases 56 Figure 38 Issue Width per Processing Element Versus Number of Processing Elements 58 Figure 39 Number of Processing Elements Versus MIPS log scale 59 Figure 40 Comparison of Multiple Thread Support among Network Processors 63 Figure 41 Map of Network Processor Market 65 ii Understanding Network Processors List of Tables Table 1 Applications and their kernels part 1 24 Table 2 Applications and their kernels part 2 25 Table 3 Applications and their kernels part 3 26 Table 4 Characteristics of the 3 major NP markets 55 Table 5 Comparison of Network Processing Planes 56 Table 6 Specialized Hardware Employed by Network Processors 62 Table 7 Micro architectural Comparison of NPs 80 Table 8 Architectural Comparison of NPs 82 Table 9 Comparison of Software Support for NPs 84 Table 10 Comparison of Memory for NPs 86 Table 11 Comparison of Physical Implementation for NPs 87 Table 12 Mapping of Applications onto Architectures part 1 88 Table 13 Mapping of Applications onto Architectures part 2 89 iii Understanding Network Processors 0 Intended Audience This document presents a survey and analysis of network processors It is intended primarily for four major audiences Network processor architects who want to know the technical details about current network processor offerings Network processor product managers who want to know the features performance and range of target applications of their competitors products Users of network processors who want to incorporate them into their products but are having trouble choosing which device best suits them Developers and designers in network processor related fields like network processing software network co processors and network testing equipment Page 1 of 89 Understanding Network Processors 1 Introduction The bandwidth explosion of the past couple years has impacted every part of our lives and this exponential growth will continue for many more years The dropping cost of bandwidth allows the masses to take full advantage of the connectivity the Internet provides This will result in more bandwidth hungry and computationally intensive applications like Voice over IP VoIP streaming audio and video Peer to Peer P2P applications Virtual Private Networks VPNs and many others that we have not even thought of yet For networks to effectively handle these new applications they will need to support new protocols that include differentiated services security and various network management functions While networks are demanding equipment with very high throughput they also need the flexibility to support new protocols and applications In addition the everchanging requirements of network equipment require solutions that can be brought to market quickly Today s legacy network implementations are based on Field Programmable Gate Arrays FPGAs for lower level processing and General Purpose Processors GPPs for higher layer processing Neither of these solutions meets all the requirements that network processing demands Consider the broad categories of alternatives for system implementation ASIC Application Specific Integrated Circuit any hardwired solution ASIP Application Specific Instruction Processor an instruction set processor specialized for a
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