Interconnect Parasitic Extraction Speaker Wenjian Yu Tsinghua University Beijing China Thanks to J White A Nardi W Kao L T Pileggi Zhenhai Zhu Outline Introduction to parasitic extraction Resistance extraction Capacitance extraction Inductance and impedance RLC extraction 2 Introduction to Parasitic Extraction 3 Introduction Interconnect conductive path Ideally wire only connects functional elements devices gates blocks and does not affect design performance This assumption was approximately true for large design it is unacceptable for DSM designs 4 Slides courtesy A Nardi UC Berkeley Introduction Real wire has Resistance Capacitance Inductance Therefore wiring forms a complex geometry that introduces capacitive resistive and inductive parasitics Effects Impact on delay energy consumption power distribution Introduction of noise sources which affects reliability To evaluate the effect of interconnects on design performance we have to model them 5 Slides courtesy A Nardi UC Berkeley Conventional Design Flow Funct Spec RTL Behav Simul Logic Synth Stat Wire Model Front end Gate level Net Gate Lev Sim Back end Floorplanning Parasitic Extrac Place Route Layout 6 Slides courtesy A Nardi UC Berkeley From electro magnetic analysis to circuit simulation Parasitic extraction Electromagnetic analysis Panel with uniform charge Filament with uniform current Thousands of R L C Model order reduction Reduced circuit 7 Challenges for parasitic extraction Parasitic Extraction As design get larger and process geometries smaller than 0 35 m the impact of wire resistance capacitance and inductance aka parasitics becomes significant Give rise to a whole set of signal integrity issues Challenge Large run time involved trade off for different levels of accuracy Fast computational methods with desirable accuracy 8 Resistance Extraction 9 Outline Introduction to parasitic extraction Resistance extraction Problem formulation Extraction techniques Numerical techniques Other issues Capacitance extraction Inductance and RLC extraction 10 Resistance extraction Problem formulation A simple L structure W V rL rL R i S HW Two terminal structure V R i A H i V It s a single R value Multi terminal port structure NxN R matrix 11 B i Resistance extraction Extraction techniques Square L R RW W counting Analytical approximate formula For simple corner structure 2 D or 3 D numerical methods For multi terminal structure current has irregular distribution Solve the steady current field for i under given bias voltages Set V1 1 others all zero flowing out current 1 i1k R1k Repeating it with different settings 12 Resistance extraction Extraction techniques numerical method to calculate the flowing out current Field solver Field equation and boundary conditions How Laplace equation inside conductor 2 2 2 u u u 2 u 2 2 2 0 x y z s u 0 divergence E Boundary conditions port surface Guk u is known Normal component other surface is zero current can not flow out En u 0 n The BVP of Laplace equation becomes solvable 13 Resistance extraction Numerical methods for resistance extraction Methods for the BVP of elliptical PDE 2 u 0 Finite ui 1 j k 2ui j k ui 1 j k 2u 2 Derivative finite difference x Dx 2 Generate sparse matrix for ODE and PDE Finite difference method element method Express solution with local support basis functions construct equation system with Collocation or Galerkin method Widely used for BVP of ODE and PDE Boundary element method Only discretize the boundary calculate boundary value Generate dense matrix with fewer unknowns For elliptical PDE 14 Resistance extraction Where are expensive numerical methods needed Complex onchip interconnects Wire resistivity is not constant Complex 3D geometry around vias Substrate coupling resistance in mixed signal IC 15 Resistance extraction All these methods calculate DC resistance Suitable for local interconnects with small dimensions or analysis under lower frequency R at high frequency estimated with skin depth for simple geometry extracted with complex methods along with L Reference W Kao C Y Lo M Basel and R Singh Parasitic extraction Current state of the art and future trends Proceedings of IEEE vol 89 pp 729 739 2001 Xiren Wang Deyan Liu Wenjian Yu and Zeyi Wang Improved boundary element method for fast 3 D interconnect resistance extraction IEICE Trans on Electronics Vol E88 C No 2 pp 232240 Feb 2005 16 Capacitance Extraction 17 Outline Introduction to parasitic extraction Resistance extraction Capacitance extraction Fundamentals and survey Volume discretization method Boundary element method Inductance and RLC extraction 18 Capacitance extraction Problem formulation A parallel plate capacitor Voltage V f1 2 Q and Q are induced on both plates Q is proportional to V The ratio is defined as C C Q V If the dimension of the plate is large compared with spacing d Other familiar capacitors interdigital capacitor 19 coaxial capacitor Capacitance extraction Problem formulation Capacitance exists anywhere Single conductor can have capacitance Conductor sphere N conductor system capacitance matrix is defined Q C U Coupling capacitance Total capacitance Electric potential 20 Capacitance extraction Interconnect capacitance extraction Only simple structure has analytical formula with good accuracy Different from resistance capacitance is a function of not only wire s own geometry but its environments All methods have error except for considering the Shield whole chip But electrostatic has locality character window Stable model Technique classification analytical and 2 D methods C unit length 2 D method ignores 3 D effect using numerical technique to solve cross section geometry 21 Capacitance extraction Interconnect capacitance extraction analytical and 2 D methods 2 5 D methods fringing parallel From Digital Integrated Circuits 2nd Edition Copyright 2002 J Rabaey et al Error 10 Commercial lateral tools Task full chip full path extraction Goal error 10 runtime overnight for given process 22 Capacitance extraction Interconnect capacitance extraction Commercial tools pattern matching Geometric parameter extraction According to given process generate geometry patterns and their parameters Build the pattern library Field solver to calculate capacitances of pattern This procedure may cost one week for a given process Calculation of C for real case Chop the layout into pieces Pattern matching Combine pattern capacitances Error Cadence Fire Ice Synopsys Star RCXT Mentor Calibre xRC pattern
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