Microprocessor Packaging The Key Link in the Chain Koushik Banerjee Technical Advisor Assembly Technology Development Intel Corporation 1 Microprocessors 1971 2001 2 Global Packaging R D China Shanghai Arizona Chandler Philippines Cavite Malaysia Penang Virtual Virtual ATD ATD 3 Main R D facility in Chandler AZ 4 Computing needs driving complexity First to introduce organic in mainstream CPUs First to introduce flip chip in mainstream CPUs Intel 486TM Pentium Processor Processor Pentium Pro Pentium II Processor Processor 25 MHz Ceramic To Organic Pentium III Processor Pentium 4 Processor Itanium Processor 1 0 GHz Wire bond To Flip Chip 5 Looking ahead Complexity and Challenges to support Moore s Law 1 Silicon to package interconnect 2 Within package interconnect 3 Power management 4 Adding more functionality Goal Goal Bring Bring technology technology innovation innovation into into High High volume volume manufacturing manufacturing at at aa LOW LOW COST COST 6 Silicon Package Relationship Anatomy 101 Silicon Processor The brain of the computer generates instructions Packaging The rest of the body Communicates instructions to the outside world adds protection No No Package Package No No Product Product Great Great Packaging Packaging Great Great Products Products 7 The Key Link in the Chain Transistor to Transistor Ckt Blk to Ckt Blk Opportunity Opportunity Innovative Innovative efficient efficient high high performance performance lowlowcost cost packages packages are are aa significant significant competitive competitive advantage advantage Chip to Package Packageto Board Board to System 8 Example Enabling Custom solutions Silicon Silicon Enabler Enabler Value ValueAdd Add custom custom solutions solutionsbased based on onmarket marketsegment segment 9 Breaking Barriers to 1 Billion Moore s Law Transistors K 1 000 000 Pentium 4 Processor 100 000 Pentium II Processor 10 000 Pentium Processor 1 000 Pentium III Processor Pentium Pro Processor i486 Processor i386 Processor 100 80286 The TheNumber Numberof ofTransistors TransistorsPer Per Chip Chipwill willDouble DoubleEvery Every18 18 Months Months 8086 10 1 75 80 85 90 95 00 05 10 15 Source Intel Integrated Integrated Packaging Packaging Silicon Silicon Technology Technology development development is is essential essential 10 Challenge 1 Silicon to package interconnect 11 Number of flip chip bumps Approaching 10K flip chip bumps on a die Flip Chip C4 interconnect Underfill 10K Silicon Package 0 ItaniumTM Pentium III Family Family Future Pentium 4 generations Family Driver Driver increased increased silicon silicon functionality functionality 12 Solution Aggressive Bump Pitch Scaling to keep down Solder die size Bumps Key Challenges Human Hair Strand Plating bumps Chip Attach Process Underfill Joint integrity HVM scalable process 13 Which leads us to Challenge 2 Within package Interconnect 14 Solution High Density Interconnect Very high escape routing density from the die Package Traces Driver Driver Need Need high high wiring wiring density density Lines narrower than hair Human Hair 15 Dimensional Stack Up Line in Silicon 130 nm 100X magnification Line in Package 25 um 100X magnification Line in Motherboard 5 mils 0 005 100X magnification 16 of micro vias in package Approaching 40K micro vias inside a package Micro vias 40K Chip Attach Pads 0 Pentium III Family Pentium 4 Family ItaniumTM Family Package X section Future generations Driver Driver High High I O I O count count power power supply supply 17 Solution Advanced lithography new term in packaging Wire C A pads Key Challenges Developing HDI high density interconnect at LOW COST High Volume Manufacturing Capable Via Build Up dielectric Core 18 Core frequency trend doubling every 2 years 100 000 10 000 1 000 Frequency MHz 100 486 10 8085 1 0 1 70 P6 Pentium proc 386 8086 286 8080 8008 4004 80 90 00 10 Source Intel Architecture Labs In addition 19 Max Mega transfers second FSB frequency ramp continues 400 66 Pentium II Processor 133 Pentium III Pentium 4 Processor Processor Future Generation Processors Microprocessor Generation 20 Solution High Performance Interconnect Technology Benefits of organic 1 Copper Low resistance 2 Low dielectric constant 3 Cheaper Key Challenge High Performance Silicon Copper Interconnects Optimize the entire substrate architecture material properties layer stack up via placement power bussing etc Organic Packaging 21 Solution Better designs A poor design can ruin processor performance Key Challenges Signal Timing Innovative routing layout Optimizing power ground distribution Co design of the complete silicon package interconnect 22 Switching gears from interconnect to Challenge 3 Power Management 23 Power Increasing silicon getting smaller Power Watts Pentium processors 100 286 8086 8085 8080 10 486 386 8008 1 4004 0 1 71 74 78 85 92 00 04 Source Intel Architecture Labs 08 Two Challenges Getting power in getting heat out 24 Importance of a quiet Power Supply High Low Ideal state High Low Reality noise OR High Low OR This is what Voltage Scaling can do 25 Need lots of charge very quickly Increasing distance from supply Hot Water Heater Inefficient design Still Waiting Close Proximity to supply 26 Solution Optimize design for power delivery Key Challenge lpkg pH Cpkg uF Cpkg Lpkg 0 18 um Generation processors 130 nm Generation processors Future Generation processors 2X improvement in capacitance and inductance needed generation Need to optimize the complete silicon package integrated power delivery solution 27 Solution Reduce system design burden heat removal Temp Silicon Tj Temp Package Case T c Temp Ambient Ta Temperature Gradient Packaging Provide Solutions for this interface of the budget OEM Provide Solutions for this interface of the budget Integrated Integrated Thermal Thermal Solutions Solutions in in the the package package reduce reduce heat heat flux flux easier easier to to cool cool in in the the system system 28 Example Integrated High Conductivity Heat Spreader Pentium4 High conductivity Thermal Interface Material 29 Example Itanium Schematic of of how how aa typical typical heat heat pipe pipe works works Schematic Wick Structure Water Vapor Heater Block Integrated heat pipe technology interfacing directly to the silicon Cooler Section Of Heat Pipe Evaporation Vapor Condenses Cooler Section Of Heat Pipe Heat Source Condensed water flows back through the wick structure by capillary action 30 And finally Challenge 4 Adding more
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