Interconnect and Packaging Lecture 2 Scalability Chung Kuan Cheng UC San Diego 1 Outlines I Trends of Interconnect and Packaging II Scalability References 2 I Trends of High Performance Interconnect and Packaging Year 2005 2010 2015 80 45 25 310 310 310 Cents pin 3 400 1 78 4 009 1 37 6 402 1 05 On chip MHz 5 170 12 000 Off chip MHz 3 125 29 103 Power Density w mm2 0 54 0 64 D1 2 Pitch nm Chip size mm2 Pin count 3 I Trends On Chip Interconnect Delay 5 40 times of Speed of Light 5ps mm Power Density Clock Skew Variations 5GHz Off Chip Interconnect and Packaging Number of pins limited growth Wire density scalability Speed and distance of interconnect 4 I Trends On chip Global Interconnect trend Concerns Speed Power Cost Reliability 5 I Trend Scalability Latency Bandwidth Attenuation Phase Velocity Distortion Intersymbol Interference Jitter Cross Talks Clock Distribution Skew Jitter Power Consumption IO Interface Density Impedance Matching Cross Talks Return loops 6 II Scalability Interconnect Models Voltage drops through serial resistance and inductance Current reduces through shunt capacitance Resistance Shunt increases due to skin effect conductance is caused by loss tangent 7 II Scalability Interconnect Models Telegrapher s equation dV z t dI z t RI z t L dz dt dI z t dV z t C GV z t dz dt Propagation Constant R j L G j C j Wave Propagation V z t V0 e z j z j t v z t Characteristic Impedance Z R j L G j C 8 II Scalability of Physical Dimensions R p A p wt Z u e 1 2 ln b w t w C v Z L Z v b t p resistivity of the conductor u magnetic permeability e dielectric permittivity v speed of light in the medium w 9 II Scalability of Physical Dimensions Resistance Increases quadratically with scaling e g p 2um cm R 0 0002ohm um at A 10umx10um R 0 02ohm um at A 1umx1um R 2ohm um at A 0 1umx0 1um Characteristic Impedance No change Capacitance per unit length No change Inductance per unit length No change 10 II Scalability of Frequency Ranges 1 RC Region 2 LC Region 3 Skin Effect 4 Loss Tangent 11 II Scalability of Frequency Ranges 1 RC Region R L G 0 j R j L G j C j RC RC 2 j RC 2 R 2 Z v jwC RC e g on chip wires R 2ohm um A 0 01um2 L 0 3pH um C 0 2fF um R L 0 67x1012 12 II Scalability of Frequency Ranges RC Region Elmore delay model with buffers inserted in intervals rn rwcw 2 ltr Delay ltr cwl s 1 f c g l rw sc g l s 2 l ltr ltr length from transmitter to receiver l interval between buffers l rn nmos resistance rs rn s cn nmos gate capacitance cg 1 g cn g is pn ratio c1 sfcg cwl 2 rw wire resistance unit length cw wire capacitance unit length r1 rwl f cd cg c2 cwl 2 scg 13 II Scalability of Frequency Ranges RC Region Elmore delay model with buffers inserted in intervals rn rwcw 2 ltr Delay ltr cwl s 1 f cg l rw scg l s 2 l Optimal interval l 2 1 f rncg rwcw Optimal buffer size Optimal delay rn cw s rwcg Delay ltr ltr 2 2 1 f rn rwcg cw 14 II Scalability of Frequency Ranges Example w 85nm t 145nm rn 10Kohm cn 0 25fF cg 2 34xcn 0 585fF rw 2ohm um cw 0 2fF um Optimal interval l 2 1 f rn c g rwcw 242 m Optimal buffer size Optimal delay rn cw s 41 rwc g Delay ltr ltr 2 2 1 f rn rw c g cw 194 fs m 194 ps mm 15 II Scalability of Frequency Ranges RC Region Year On Chip 2005 2010 2015 rncn ps 0 86 0 39 0 18 rwcw ps mm 284 616 1510 l um 168 77 33 D ps um 0 096 0 095 0 101 no scattering p 2 2uohm cm 16 II Scalability of Frequency Ranges RC Region Device delay rncn decreases with scaling Wire delay rwcw increases with scaling Interval l between buffers decreases with scaling In order to increase the interval we add the stages of each buffer 17 II Scalability of Frequency Ranges 2 LC Region R L G 0 j R j L G j C R R j L j C j LC 2Z Z L v 1 LC C 18 II Scalability 3 Skin Effect Skin Depth R 2 Z 2 e g 0 7um f 10GHz p 2uohm cm For 100umx25um RDC 0 000008ohm um 8ohm m R 0 000114ohm um 114ohm m 19 II Scalability 4 Loss Tangent 0 1 j tan C C0 G C0 tan j R j L G j C R GZ j LC 2Z 2 C0 0 2 fF m 5 109 Z 50 tan p 0 02 GZ 2 6 m polyimide tan g 0 002 GZ 2 0 6 m glass tan q 0 0002 GZ 2 0 06 m quartz 20 References E Lee et al CMOS High Speed I Os Present and Future ICCD 2003 http www itrs net Common 2004Update 2004Update htm G A Sai Halasz G A Performance Trends in High End Processors IEEE Proceedings pp 20 36 Jan 1995 M T Bohr Interconnect scaling the real limiter to high performance ULSI Electron Devices Meeting 1995 International 10 13 Dec 1995 pp 241 244 21
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