A Building Block Approach to Sensornet Systems Prabal Dutta Jay Taneja Jaein Jeong Xiaofan Jiang and David Culler Computer Science Division University of California Berkeley Presented by Gautham Reddy What is the paper about Proposes to reduce the hardware platform development time to result Time to result Prototype Pilot Production What it proposes Building block approach to the hardware platform How to go about it Partitioning functionality between modules and carriers and identify guidelines for their interconnection Architecture should support the 3 stages of design BACKGROUND Earlier approaches remain inadequate Did not answer all stages Examples for ineffective approaches Mica2Dot Telos iMote BTnode Eyes TIP TinyNode Sensinode IRIS MICAz Stamp and kMote MASS and mPlatform BUILDING BLOCK APPROACH The heart of the system are Module General purpose Carrier Application specific Modules are reusable self contained subsystems in a multi chip module MCM package Carriers are custom circuit board general purpose modules application specific components EPIC Family Core module Microcontroller Radio IEEE 802 15 4 Flash memory 48 bit unique serial identier U FL RF connector The Epic Core module A microcontroller radio and flash Core Prototype Pilot Production Easy to Easy to design Must provide performance Use at the CAD level comparable to commercial Debug simple to hand solder modules Profile flexible with antenna choice Have an attractive cost Easy to program and profile debug Component choices Microcontroller MSP430F1611 ATmega1281 Requirements low active current wide operating voltage range 16 bit 8 bit 16 bit sleep timer Fast wakeup from sleep 10kB 4kB large amount of RAM DMA channels that can operate while the CPU sleeps Radio CC2520 RF230 Requirements radio idle listening receive sensitivity transmit power CC2520 has a dedicated pin for conveying the clear channel assessment C signal to the microcontroller which reduces the channel polling time Mechanical Design What form factor and connector interface should the module use LCC 68 Reasons The package is leadless hence no costs are incurred on connectors Easy to solder semi holes Easier debugging breakout boards used EXPERT PERIPHERAL MODULES 1 Gbit NAND flash 16 Mbit NOR flash 512 Kbit FRAM host interface reprogramming JTAG over USB battery charging Guidance for partitioning functionality between modules and carriers Deep expertise Specialized equipment Reuse in modular form Simply more convenient to group PROTOTYPING Try It And See Debugging CARRIER BOARD CASE STUDIES External Sensor and Solar EPIC Telos Cost 10 83 11 59 Form factor better larger exposed GIO and ADC pins better insufficient AC Power Monitoring Cost 26 40 which is significantly lesser than the previous versions Testbed Replacement DISCUSSION Since the modules are general purpose it makes sense to reuse by sharing the libraries There is little or no overlap in electronic parts between modules and carriers This implies that both modules and carriers are best optimized CONCLUSION How does the building block approach solve the problem It supports many physical interconnects Separates the Carriers from Modules Modules are predesigned Questions
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