Exploring SoC Communication Architectures for Performance and Power Nikil Dutt ACES Laboratory Center for Embedded Computer Systems Donald Bren School of Information and Computer Sciences University of California Irvine dutt uci edu http www ics uci edu aces Outline Motivation CA Exploration at Transaction Level Floorplan aware Bus Architecture Synthesis Approach SoC Power Energy Modeling Design Drivers Summary Copyright 2006 UCI ACES Laboratory http www cecs uci edu aces UCSD Talk Feb 13 2006 2 100M Logic Transistors Chip Transistor Staff Month 1B 10M 58 Yr compound Complexity growth rate 100M 10M 1M 100K 1M 10K 100K 1K 100 10 2009 2007 2005 2003 2001 1999 1997 1995 1991 1989 1987 1985 1983 1K 1993 21 Yr compound Productivity growth rate 10K Productivity Transistors Staff Month 10B 1981 Complexity Logic Transistors per Chip K SoC Design Complexity vs Productivity Source SEMATECH SoC designs today are complex characterized by more and more IPs being integrated on a single chip and a shrinking time to market Copyright 2006 UCI ACES Laboratory http www cecs uci edu aces UCSD Talk Feb 13 2006 3 Strategies to handle SoC complexity IP based design and reuse design IPs to be reused in multiple designs requires initial investment to create reusable cores but productivity in subsequent designs can be substantially enhanced with reuse e g VSIA and OCP IP core interface standards Raising modeling abstraction simulating design at RTL level for verification or exploration is just not practical anymore capturing the system hardware and software at a higher level of abstraction is better faster to model quicker to simulate early design visibility reduces time to market models are typically captured in C C SystemC Copyright 2006 UCI ACES Laboratory http www cecs uci edu aces UCSD Talk Feb 13 2006 4 Ideal Platform based SoC Design Flow application requirements algorithm algorithmselection selection optimization optimization functional model HW SW HW SWpartitioning partitioning behavior behaviormapping mapping architecture exploration architecture exploration M IP CPU CPU S S M IP M CPU S communication model interface interfacesynthesis synthesis cycle scheduling cycle scheduling IP implementation model Copyright 2006 UCI ACES Laboratory IP M CPU architecture model CA CAselection exploration selection exploration protocol protocolgeneration generation topology synthesis topology synthesis OUTPUT INPUT Logic synthesis and physical implementation http www cecs uci edu aces S CPU M IP S IP CPU M S UCSD Talk Feb 13 2006 5 Data Flow Replacing Data Processing As Major SoC Design Challenge P Core 1 SoCs Core 2 Circa 2002 Core N Critical Decision Was uP Choice Exploding core counts requiring more advanced Interconnects EDA cannot solve this architectural problem easily Complexity too high to hand craft and verify Main Bus P P Mem Bus Sub system I O Bus DRAMC SoCs Circa 2005 Critical Decision Is Interconnect Choice Communication Architecture Design and Verification becoming Highest Priority in Contemporary SoC Design Copyright 2006 UCI ACES Laboratory http www cecs uci edu aces UCSD Talk Feb 13 2006 6 Source SONICS Inc Need for Communication centric Design Flow communication architecture consumes upto 50 of total on chip power communication is THE most critical aspect affecting system performance ever increasing number of wires repeaters bus components arbiters bridges decoders etc increases system cost communication architecture design customization exploration verification and implementation takes up the largest chunk of a design cycle Communication Architectures in today s complex systems significantly affect performance power cost and time to market Copyright 2006 UCI ACES Laboratory http www cecs uci edu aces UCSD Talk Feb 13 2006 7 Evolution of On chip Communication Architectures Network on chips bus matrix hierarchical bus shared bus custom 1990 time 1995 2000 Copyright 2006 UCI ACES Laboratory http www cecs uci edu aces 2005 2010 UCSD Talk Feb 13 2006 8 Evolution of On chip Communication Architectures Network on chips bus matrix hierarchical bus shared bus custom 1990 time 1995 2000 2010 2005 Focus of this talk Copyright 2006 UCI ACES Laboratory http www cecs uci edu aces UCSD Talk Feb 13 2006 9 SoC Bus based Communication Architectures IP IP IP IP IP IP IP IP IP a single bus IP IP IP BRIDGE IP IP b hierarchical bus IP IP IP IP IP IP IP IP IP IP c multiple bus IP IP IP IP IP IP d split bus IP IP IP IP e point to point bus Copyright 2006 UCI ACES Laboratory http www cecs uci edu aces IP IP f bus matrix UCSD Talk Feb 13 2006 10 Bus Terminology Master or Initiator Slave or Target Controls access to the shared bus Uses arbitration scheme to select master to grant access to bus Decoder IP component that does not initiate transfers and only responds to incoming transfer requests Arbiter IP component that initiates a read or write data transfer Determines which component a transfer is intended for Bridge Connects two busses Acts as slave on one side and master on the other Copyright 2006 UCI ACES Laboratory http www cecs uci edu aces UCSD Talk Feb 13 2006 11 Modern SoC Design Flow algorithm selection optimization allocation behavior partitioning scheduling protocol selection channel partitioning arbitration Product Productrequirements requirements from fromcustomer customer Specification SpecificationModel Model Architecture ArchitectureModel Model Communication CommunicationModel Model cycle scheduling protocol scheduling Copyright 2006 UCI ACES Laboratory http www cecs uci edu aces Implementation ImplementationModel Model UCSD Talk Feb 13 2006 12 Bus based Communication Architectures Several bus based CA commonly used in SoC designs AMBA Wishbone CoreConnect PowerPC Bus Key Features High Performance System Bus processors memory DMA etc Low Bandwidth Peripheral Bus timer interrupt controller UART etc Copyright 2006 UCI ACES Laboratory http www cecs uci edu aces UCSD Talk Feb 13 2006 13 Outline Motivation CA Exploration at Transaction Level Floorplan aware Bus Architecture Synthesis Approach SoC Power Energy Modeling Design Drivers Summary Copyright 2006 UCI ACES Laboratory http www cecs uci edu aces UCSD Talk Feb 13 2006 14 Issues Selecting and configuring busbased CA for optimal performance is a critical activity in a SoC design requiring CA exploration PE Interface Interface bus architecture e g PPC Bus AMBA CoreConnect architecture parameters e g bus width burst size bus topologies e g shared
View Full Document
Unlocking...