Hardware Design with VHDL PLDs II ECE 443ECE UNM 1 (9/2/08)Origins of FPGAsXilinx introduced first FPGA in ’84, but engineers didn’t embrace them until early’90s.History:• ’47: Shockley, et. al. introduce first transistor at Bell Labs.• ’50: Bipolar junction transistor (BJT) introduced.• ’62: Hofstein, et. al. introduce metal-oxide semiconductor field-effect transistor(MOSFET) at RCA.• ’58: Jack Kilby introduced the integrated circuit.• ’70: Intel introduced 1024-bit DRAM, Fairchild introduced 256-bit SRAM.• ’71: Intel introduced first microprocessor, 4004.• ’70: PLDs introduced, later CPLDs.PLDsSPLDs CPLDsPROMs PLAs PALs GALs etc.The Design Warrior’s Guide to FPGAs,ISBN 0750676043,Copyright(C) 2004 Mentor Graphics CorpHardware Design with VHDL PLDs II ECE 443ECE UNM 2 (9/2/08)PROMsThe first of the simple PLDs were PROMs (around ’70).The programmable links in the OR array can be implemented as fusible links or asEPROM/EEPROM transistors.a b c&!a & !b & !cor or orw x yAddr 0&!a & !b & cAddr 1&!a & b & !cAddr 2&!a & b & cAddr 3&a & !b & !cAddr 4&a & !b & cAddr 5&a & b & !cAddr 6&a & b & cAddr 7These connectionsare selectivelyprogrammedPre-wired AND arrayProgrammableOR arrayEach AND has 3 inputsORs have 8 inputssum-of-productsformThe Design Warrior’s Guide to FPGAs,ISBN 0750676043,Copyright(C) 2004 Mentor Graphics CorpHardware Design with VHDL PLDs II ECE 443ECE UNM 3 (9/2/08)PROMsPROMs were originally intended for use as computer memories to store programsand constant data.However, engineers used them to implement lookup tables and state machines.PROMs can be used to implement any block of combinational logic.Programming these functions is a simple matter of choosing the correct links in theOR array.NOTE: Real PROMs have significantly more inputs and outputs.abcwxya b c0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 10 1 00 1 10 1 00 1 10 1 00 1 11 0 11 0 0w x yThe Design Warrior’s Guide to FPGAs,ISBN 0750676043,Copyright(C) 2004 Mentor Graphics CorpHardware Design with VHDL PLDs II ECE 443ECE UNM 4 (9/2/08)PLAsAn important limitation of PROM is that the AND plane produces all productswhether they are used or not -- this limits the number of inputs.Programmable Logic Arrays (PLAs) allowed both the AND and OR plane to be pro-grammed.Here the number of AND functions in the AND array in independent of the numberof inputs to the device.The Design Warrior’s Guide to FPGAs,ISBN 0750676043,Copyright(C) 2004 Mentor Graphics CorpProgrammableAND arrayHardware Design with VHDL PLDs II ECE 443ECE UNM 5 (9/2/08)PLAsThe following example illustrates the implementation of 3 functions, w, x and y.Note that product terms can be shared among output functions.The programmable links slow signals -- thus PLAs are slower then PROMsPLAs never achieved any significant level of market presence.The Design Warrior’s Guide to FPGAs,ISBN 0750676043,Copyright(C) 2004 Mentor Graphics CorpProgrammableAND arrayOne variantuses a NORarray instead.Hardware Design with VHDL PLDs II ECE 443ECE UNM 6 (9/2/08)PALsProgrammable Array Logic (PALs) were introduced in late 70’s to address speedproblem of PLAs.Here, the AND array is programmable and the OR array is predefined, therefore theyare faster than PLAs.However, PALs only allow a restricted number of product terms to be OR’ed, at leaston chip.The Design Warrior’s Guide to FPGAs,ISBN 0750676043,Copyright(C) 2004 Mentor Graphics CorpHardware Design with VHDL PLDs II ECE 443ECE UNM 7 (9/2/08)PALsReal devices have many more inputs and outputs plus a variety of options availableincluding:• The ability to invert the outputs• The ability to tristate the outputs• The ability to latch the outputs• The ability to configure certain pins as input or output.CPLDsIn ’84, Altera introduced a CPLD based on a combination of CMOS andEPROM technologies.CMOS allowed low power and high density while EPROM enabled thesedevices to be used for development and prototyping.Altera’s real contribution was to use an interconnection array with less than100% connectivity.This increased complexity of software but keep the device scalable in termsof speed, power and cost.Hardware Design with VHDL PLDs II ECE 443ECE UNM 8 (9/2/08)CPLDsA generic CPLD structure typically consists of several SPLD blocks sharing a com-mon programmable interconnection matrix.Both the SPLDs and the interconnect can be programmed.Interconnection matrix usually has more wires than the individual SPLD blocksTherefore, a MUX is used to connect them.The programmable switches may be EPROM, EEPROM, FLASH or SRAM based.The Design Warrior’s Guide to FPGAs,ISBN 0750676043,Copyright(C) 2004 Mentor Graphics CorpHardware Design with VHDL PLDs II ECE 443ECE UNM 9 (9/2/08)JEDEC, etc.In the early days, the design flow consisted of a hand-drawn schematic diagram thatwas later converted to tabular format and typed into a file.The file (used by the device programmer) defined which fuses were to be blown (orwhich antifuses were to be grown).Each PLD vendor developed its own file format, which made this task time consum-ing and error prone.The Joint Electron Device Engineering Council (JEDEC) intervened and defined astandard language that everyone adopted.PAL Assembler (PALASM) was also developed and allowed designers to specify thefunction in a sum-of-products form.PALASM read the HDL src file and generated the text programming file.PALASM and other early HDLs laid the foundation for Verilog and VHDL, and syn-thesis tools used today for ASIC and FPGA designs.Hardware Design with VHDL PLDs II ECE 443ECE UNM 10 (9/2/08)ASIC (gate array, etc.)Four main classes exist today, in order of increasing complexity:• Gate arrays• Structured ASICs• Standard cell devices• Full-custom chipsIn order of appearance.Full-customIn the early days, only two classes of chips existed.• Standard off-the-shelf components• Full-custom ASICs (such as microprocessors)For the full-custom class, nothing is predefined, not even standard logic gates.All wires and gates are hand-crafted individually, and optimized for speed, areaand power.Hardware Design with VHDL PLDs II ECE 443ECE UNM 11 (9/2/08)ASIC (gate array, etc.)Gate arrays are based on the idea of a basic cell consisting of a collection of uncon-nected transistors and resistors.The ASIC vendor prefabricates silicon chips containing arrays of these basic cells.Channels are typically provided between rows or