Hardware Design with VHDL Design Example: SRAM ECE 443ECE UNM 1 (12/3/08)External SRAMA common type of system RAM is asynchronous static RAM (SRAM).Access is more complicated than internal memory -- here data, address and controlsignals must be asserted in a specific order and held for a specific time.A memory controller is usually used to shield the synchronous system from SRAM.It is responsible for generating the properly timed signals and making theSRAM look ’synchronous’.Its performance is measured by the number of memory accesses that can becompleted in a given time period.Designing a memory controller that is optimal is non-trivial.This set of slides demonstrates the development of a memory controller.Note that the timing characteristics of an SRAM will differ depending on themanufacturer, but the same basic principles apply.Hardware Design with VHDL Design Example: SRAM ECE 443ECE UNM 2 (12/3/08)External SRAMYour boards do NOT have external SRAM installed by default but it is available onan expansion card.We have Digilent Memory Modules, C2: 1Mb SRAM, no Flash available.These expansion cards have two banks of ISSI IS61LV5128AL 512K x 8SRAMHigh-performance, low-power CMOS process with 10 ns access times.Single 3.3V power supply, static operation: no clock or refresh required.Easy memory expansion with CE (power down) and OE options.A0-A18Decoder512K X 8Mem arrayColumn I/OI/Odata circuitControlcircuitCEOEWEFunctionalBlock DiagramI/O0-I/O7Hardware Design with VHDL Design Example: SRAM ECE 443ECE UNM 3 (12/3/08)External SRAMTruth Table:This device has a 19-bit address bus (A0-A18), a bi-directional 8-bit data bus (I/O0-I/O7) and three active low control signals, CE, OE and WE (see table above).The timing characteristics of an asynchronouns SRAM are complex and involvemore than 24 parameters -- here we focus on only a few key parameters.For reading:• tRC: read cycle time, the min time between two read operations (min 10 ns).• tAA: address access time, the time required to obtain a stable output data after anaddress change (max 10 ns).• tOHA: output hold time, the time that the output data remains valid after the addresschanges (min 2 ns).Mode WE CE OE I/O operationNot selected (power-down) XH X High-ZOutput disabled HL H High-ZRead HL L DoutWrite LL X DinHardware Design with VHDL Design Example: SRAM ECE 443ECE UNM 4 (12/3/08)SRAM Read Timing Parameters• tDOE: output enable access time, the time required to obtain valid data after the OEis activated (max 4 ns).• tHZOE: output enable high-Z time, the time for the tri-state buffer to enter the high-impedance state after OE is deactivated (max 4 ns).• tLZOE: output enable to low-Z time, the time for the tri-state buffer to leave the high-impedance state afterOE is activated (min 0 ns).Reading can be accomplished in two ways, with OE activated, changing the addresswill change the data; second, OE can be used (for interleaved read/writes).Timing diagram for address-controlled read cycleAddressDouttRCtOHAtAAdata validtOHAprevious data validHardware Design with VHDL Design Example: SRAM ECE 443ECE UNM 5 (12/3/08)SRAM Read and Write Timing ParametersTiming diagram for OE controlled read cycle timeFor write operations, the following specs are important:• tWC: write cycle time, the minimal time between two write operations (min 10 ns).• tSA: address setup time, the minimal time that the address must be stable before WEis activated (min 0 ns).• tHA: address hold time, the minimal time that the address must be stable afterWE isdeactivated (min 0 ns).AddressOEtRCtAAtOHADoutHIGH-Zdata validtDOEtLZOEtHZOEHardware Design with VHDL Design Example: SRAM ECE 443ECE UNM 6 (12/3/08)SRAM Read and Write Timing Parameters• tPWE1: WE pulse width, the minimal time that WE must be asserted (min 8 ns).• tSD: data setup time, the minimal time that data must be stable before the latchingedge (the edge in which WE changes from 0 to 1) (min 6 ns).• tHD: data hold time, the minimal time that data must be stable after the latchingedge (min 0 ns).Data sheet gives several timing diagrams for write, this one forWE controlledAddresstWCtSAWEtPWE1tHADindatain validtSDtHDHardware Design with VHDL Design Example: SRAM ECE 443ECE UNM 7 (12/3/08)Memory ControllerBlock diagram of memory controller• mem: asserted to 1 to initiate a memory operation.• rw: specifies read (1) or write (0) operation• addr: is a 19-bit address• data_f2s: 8-bit data to be written to SRAM.• data_s2f_r: 8-bit registered data retrieved from SRAM• data_s2f_ur: 8-bit unregistered data retrieved from SRAM• ready: status signal indicating whether the controller is ready to accept a new com-mand -- needed b/c memory operation may take more than 1 clock cycle.mainsystemaddrmemorycontrollerdata_f2sdata_s2f_rdata_s2f_urmemr/wready512 X 8SRAMadWEOEdioCE0Hardware Design with VHDL Design Example: SRAM ECE 443ECE UNM 8 (12/3/08)Memory ControllerThe memory controller provides a ’synchronous’ wrap around the SRAM.When the main system wants to access memory, it places the address and data (forwrites) on the bus and activates mem and rw signals.On the rising edge of clock, all signals are sampled by the memory controller and theoperation is performed.For reads, the data becomes available after 1 or 2 clock cycles.FSMmemrwreadydddqqqenenenaddrdata_f2sdata_s2f_rdioaddata_s2f_urMemory Controller Block DiagramWEOEtwo readportsHardware Design with VHDL Design Example: SRAM ECE 443ECE UNM 9 (12/3/08)Memory ControllerThe data path consists of one address register and two data registers, which store thedata for each direction.Since the data bus, dio, is a bi-directional signal, a tri-state buffer is inserted.The FSM defines the control path which is constrained by the timing specs.Consider the control sequence for a read operation:Here, WE is deactivated during the entire operation.• Place the address on the ad bus and activate the OE signal.• Wait for at least tAA. The data from the SRAM becomes available after thisinterval.• Retrieve the data from dio and deactivate the OE signal.For a write operation:• Place address on ad bus and data on dio bus and activate WE signal.• Wait for at least tPWE1.• DeactivateWE -- data is latched to SRAM on 0 to 1 transition.• Remove data from the dio bus.Hardware Design with VHDL Design Example: SRAM ECE 443ECE UNM 10 (12/3/08)Memory ControllerNote that tHD (data hold time after write ends) is 0 ns for this SRAM.This means