UNM ECE 443 - ECE 443 Concurrent Stmts (33 pages)

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ECE 443 Concurrent Stmts



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ECE 443 Concurrent Stmts

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Pages:
33
School:
University of New Mexico
Course:
Ece 443 - Hardware Design With Vhdl

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Hardware Design with VHDL Concurrent Stmts ECE 443 Concurrent Signal Assignment Statements This slide set covers the concurrent signal assignment statements which include the conditional signal assignment and selected signal assignment stmts Topics include Simple signal assignment statement conditional assign without a condition Conditional signal assignment statement Selected signal assignment statement Conditional vs selected signal assignment Simple signal assignment statement signal name projected waveform For example y changes after a or b changes 10 ns y a b 1 after 10 ns Timing info ignored in synthesis and delay is used for signal name value expression ECE UNM 1 9 6 12 Hardware Design with VHDL Concurrent Stmts ECE 443 Simple Signal Assignment Statements Other examples status 1 even p1 and p2 or p3 and p4 arith out a b c 1 Implementation of last statement Note that this may be simplified during synthesis and that the size of the synthesized circuit can vary significantly for different stmts Also note that it is syntactically correct for a signal to appear on both sides of a concurrent signal assignment ECE UNM 2 9 6 12 Hardware Design with VHDL Concurrent Stmts ECE 443 Simple Signal Assignment Statements For example q not q and not en or d and en Here the q signal takes the value of d when en is 1 otherwise it takes the inverse of itself Although this is syntactically correct the statement forms a closed feedback loop and should be avoided It may synthesize to an internal state memory in cases where the next value of q depends on the previous value e g q q and not en or d and en Or it may oscillate as is true of the statement above This is REALLY BAD PRACTICE because the circuit becomes sensitive to internal propagation delay of its elements It also confuses the synthesis tools and complicates the testing process ECE UNM 3 9 6 12 Hardware Design with VHDL Concurrent Stmts ECE 443 Conditional Signal Assignment Statements Simplified syntax signal name value



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