Hardware Design with VHDL Concurrent Stmts ECE 443ECE UNM 1 (9/6/12)Concurrent Signal Assignment StatementsThis slide set covers the concurrent signal assignment statements, which include theconditional signal assignment and selected signal assignment stmtsTopics include• Simple signal assignment statement (conditional assign. without a condition)• Conditional signal assignment statement• Selected signal assignment statement• Conditional vs. selected signal assignmentSimple signal assignment statementsignal_name <= projected_waveform;For example-- y changes after a or b changes + 10 nsy <= a + b + 1 after 10 ns;Timing info ignored in synthesis and δ-delay is used forsignal_name <= value_expression;Hardware Design with VHDL Concurrent Stmts ECE 443ECE UNM 2 (9/6/12)Simple Signal Assignment StatementsOther examples:status <= ’1’;even <= (p1 and p2) or (p3 and p4);arith_out <= a + b + c - 1;Implementation of last statementNote that this may be simplified during synthesis and that the size of the synthesizedcircuit can vary significantly for different stmtsAlso note that it is syntactically correct for a signal to appear on both sides of a con-current signal assignmentHardware Design with VHDL Concurrent Stmts ECE 443ECE UNM 3 (9/6/12)Simple Signal Assignment StatementsFor example:q <= ((not q) and (not en)) or (d and en);Here, the q signal takes the value of d when en is ’1’, otherwise it takes the inverse ofitselfAlthough this is syntactically correct, the statement forms a closed feedback loop andshould be avoidedIt may synthesize to an internal state (memory) in cases where the next value of qdepends on the previous value, e.g.,q <= (q and (not en)) or (d and en);Or it may oscillate (as is true of the statement above)This is REALLY BAD PRACTICE because the circuit becomes sensitive to internalpropagation delay of its elementsIt also confuses the synthesis tools and complicates the testing processHardware Design with VHDL Concurrent Stmts ECE 443ECE UNM 4 (9/6/12)Conditional Signal Assignment StatementsSimplified syntax:signal_name <=value_expr_1 when boolean_expr_1 elsevalue_expr_2 when boolean_expr_2 elsevalue_expr_3 when boolean_expr_3 else...value_expr_nThe boolean_expr_i return true or false and are each evaluated from top-to-bottomuntil one is found to be trueWhen this occurs, the value_expr_i is assigned to the signal_name signalThis type of statement can be represented by a multiplexer circuitThis is the truth table for an 8-bit, 4-to-1 multiplexerHere, a, b, c, and d are input signalss is also an input, i.e., a 2-bit signal the input data to routeto the outputHardware Design with VHDL Concurrent Stmts ECE 443ECE UNM 5 (9/6/12)Conditional Signal Assignment Statementslibrary ieee;use ieee.std_logic_1164.all;entity mux4 isport(a, b, c, d: in std_logic_vector(7 downto 0);s: in std_logic_vector(1 downto 0);x: out std_logic_vector(7 downto 0));end mux4;architecture cond_arch of mux4 is begin x <= a when (s="00") else b when (s="01") else c when (s="10") else d;end cond_arch;Hardware Design with VHDL Concurrent Stmts ECE 443ECE UNM 6 (9/6/12)Conditional Signal Assignment StatementsNote that the use of std_logic data type, which has 9 possible values, makes the laststatement assign d to x under more conditions than the expected s = "11" caseIn fact, since each bit of s can assume 9 values, there are actually 9*9 = 81 conditionsfor the two bit sequence including "0Z", "UX", "0-", etcTherefore, the last statement assigns d to x under 77 (81-4) additional conditions, butthese conditions are ONLY possible in simulationsExcept for the limited use of ’Z’, the metavalues are ignored by synthesis softwareSome synthesis software allows the following alternative expression x <= a when (s="00") else b when (s="01") else c when (s="10") else d when (s="11") else ’X’;Hardware Design with VHDL Concurrent Stmts ECE 443ECE UNM 7 (9/6/12)Conditional Signal Assignment StatementsBinary decoder: An n-to2n decoder has an n-bit input and a 2n-bit output, whereeach bit of the output represents an input combinationlibrary ieee;use ieee.std_logic_1164.all;entity decoder4 isport(s: in std_logic_vector(1 downto 0);x: out std_logic_vector(3 downto 0));end decoder4;Hardware Design with VHDL Concurrent Stmts ECE 443ECE UNM 8 (9/6/12)Conditional Signal Assignment Statementsarchitecture cond_arch of decoder4 is begin x <= "0001" when (s="00") else "0010" when (s="01") else "0100" when (s="10") else "1000";end cond_arch;Both the MUX and decoder are a better match to selected signal assignment (later)Priority encoder: Checks the input requests and generates the code of the requestwith highest priorityThere are four input requests, r(3), ..., r(0)The outputs include a 2-bit signal (code), whichis the binary code of the highest priority requestand a 1-bit signal active that indicates if there isan active requestHardware Design with VHDL Concurrent Stmts ECE 443ECE UNM 9 (9/6/12)Conditional Signal Assignment StatementsThe r(3) has the highest priority, i.e., when asserted, the other three requests areignored and the code signal becomes "11"When r(3) is not asserted, the second highest request, r(2) is examinedThe active signal is to distinguish the last case, when r(0) is asserted and the case inwhich NO request is assertedlibrary ieee;use ieee.std_logic_1164.all;entity prio_encoder42 isport(r: in std_logic_vector(3 downto 0);code: out std_logic_vector(1 downto 0);active: out std_logic);end prio_encoder42;Hardware Design with VHDL Concurrent Stmts ECE 443ECE UNM 10 (9/6/12)Conditional Signal Assignment Statementsarchitecture cond_arch of prio_encoder42 is begin code <= "11" when (r(3)=’1’) else "10" when (r(2)=’1’) else "01" when (r(1)=’1’) else "00"; active <= r(3) or r(2) or r(1) or r(0);end cond_arch;The priority structure of the conditional signal assignment matches well this func-tionalityA simple ALUInput signals include ctrl, src0 and src1Output signal is resultALU performs 5 functions, 3 arithmetic and 2 BooleanThe input and output are interpreted as signedintegers when arithmetic ops are selectedHardware Design with VHDL Concurrent Stmts ECE 443ECE UNM 11 (9/6/12)Conditional Signal Assignment StatementsWe will use std_logic data type for portability reasons and convert it to the desireddata type, e.g., signed, in the architecture bodyOnce the arithmetic