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Hardware Design with VHDL FSMs ECE 443ECE UNM 1 (11/19/08)FSMsMealy vs. Moore:FSMs can be described using state diagrams or algorithmic state machines (ASMs)next statestate_nextdqstateclkMealyinputsoutputMooreoutputlogiclogicMealyoutputsMooreoutputsreg.logicstate_regstate_namemoore< = valexprmealy <= valexprmealy <= valto other state to other stateHardware Design with VHDL FSMs ECE 443ECE UNM 2 (11/19/08)State Transition Graph and ASMsState diagrams contain nodes (states) and transition arcs.The arcs are associated with a logical expression of the input signals -- whentrue, the arc is taken.Moore outputs depend only on the state and are placed inside the circles.Mealy outputs depend on the state and inputs, and are listed on the arcs.Only the asserted outputs are listed.ASMsEach state box has only one exit and is usually followed by a decision box.moore <= valstate_nameboolean cond.T Fmealy <= valconditionaloutput boxdecision boxstate boxHardware Design with VHDL FSMs ECE 443ECE UNM 3 (11/19/08)State Transition Graph and ASMsExample:This FSM has three states, two input signals a and b, a Moore output y1 and a Mealyoutput y0.y1 is asserted when in states s0 and s1. y0 is asserted when in s0 and a.b is true.y1 <= 1s0TTy0 <= 1s0y1 <= 1s1y1 <= 1aaaa.bs2a.by0 <= 1a=1Fb=1s2a=1Fy1 <= 1T Fs1Hardware Design with VHDL FSMs ECE 443ECE UNM 4 (11/19/08)State Transition Graph and ASMslibrary ieee;use ieee.std_logic_1164.all;entity fsm_ex isport(clk, reset: in std_logic;a, b: in std_logic;y0, y1: out std_logic;);end fsm_exarchitecture mult_seg_arch of fsm_ex istype ex_state_type is (s0, s1, s2);signal state_reg, state_next: ex_state_type;beginprocess(clk, reset)beginif (reset = ’1’) thenstate_reg <= s0;Hardware Design with VHDL FSMs ECE 443ECE UNM 5 (11/19/08)State Transition Graph and ASMselsif (clk’event and clk = ’1’) thenstate_reg <= state_next;end if;end process;process(state_reg, a, b)begincase state_reg iswhen s0 =>if (a = ’1’) thenif (b = ’1’) thenstate_next <= s2;elsestate_next <= s1;end if;elsestate_next <= s0;end if;Hardware Design with VHDL FSMs ECE 443ECE UNM 6 (11/19/08)State Transition Graph and ASMswhen s1 =>if (a = ’1’) thenstate_next <= s0;elsestate_next <= s1;end if;when s2 =>stat_next <= s0;end case;end process;-- Moore output logicprocess (state_reg)begincase state_reg iswhen s0 | s2 =>y1 <= ’0’;when s1 =>y1 <= ’1’;Hardware Design with VHDL FSMs ECE 443ECE UNM 7 (11/19/08)State Transition Graph and ASMsend case;end process;-- Mealy output logicprocess (state_reg, a, b)begincase state_reg iswhen s0 =>if (a = ’1’ and b = ’1’) theny0 <= ’1’;elsey0 <= ’0’;end if;when s1 | s2 =>y0 <= ’0’;end case;end process;end mult_seg_arch;Hardware Design with VHDL FSMs ECE 443ECE UNM 8 (11/19/08)FSMDAn FSMD (finite state machine with data path) combines an FSM and regularsequential logic.The FSM is referred to as the control path -- it examines the external commands andstatus and generates control signals to control the operation of the data path.FSMD are used to describe RTL (register transfer level) logic.Here, operations manipulate data and control transfer among a set of registers.Note that the result, 9 - 3 + 1 = 7 is not stored until the rising edge of clk.Also, b_reg changes after a clk-to-q delay.d qd qclk+1-a_nexta_regb_regclka_reg9357b_regHardware Design with VHDL FSMs ECE 443ECE UNM 9 (11/19/08)FSMDThe ASM chart for an RTL circuit:RTL operations are treated as output signals and are placed inside the boxes.The current state, given by state_reg, selects the MUXHere, r1 is destination register. First it is initialized to 8, and then is added to the con-tents of r2, and then shifted left by two bits.The r1 <- r1 is the default operation (no change) and is typically left out.s0 s1 s2 s3r1 <- 8r1 <- r1+r2 r1 <- r1<< 2r1 <- r1d qd q01238+<<2state_regclkr2_regr1_regr1_nextHardware Design with VHDL FSMs ECE 443ECE UNM 10 (11/19/08)FSMDAs another example:Here, the RTL operation on r2 is specified in a conditional output box.All operations, e.g., r2 + a and r2 + b are performed in parallel and the proper valueis routed to the input of r2_reg based on the condition and state_reg.r1 <- r1 - 1s0a > br2 <- r2 + ar2 <- r2 + bd q0-1d q0++state_reg01clk>abF Tr2_regr1_regr1_nextr2_nextHardware Design with VHDL FSMs ECE 443ECE UNM 11 (11/19/08)FSMDNote that the destination register is updated when the FSMD exits the current state,e.g., r_next <= r_reg - 1; r_reg <= r_next on the next rising edge of clk.Beware the delayed store:On the left, the r register is decremented in the state box and ALSO used in the deci-sion box.Since r is NOT updated until exit from the state box, the old content of r is usedin the decision box!The right side shows how to use the new value -- here the output of the combinationallogic is used (r_next) in the decision box.s1r <- r - 1r = 0FTs1r_next := r - 1r_next = 0FTr <- r_next’:=’ indicatesimmediateassignmentHardware Design with VHDL FSMs ECE 443ECE UNM 12 (11/19/08)FSMDGeneral structure of an FSMD:Although the FSMD consists of two types of sequential circuits, both are controlledby the same clock.d qdataregsroutingnetworkData pathfunctionalunitsroutingnetworkdatainputdataoutputoutputlogicControl pathd qstateregsnext-statelogiccontrol signalsinternal statusexternal statuscommandFSMHardware Design with VHDL FSMs ECE 443ECE UNM 13 (11/19/08)RTL Version of Debouncing CircuitThe FSM is used to initiate a timer so that an exact ’wait’ interval can be imple-mented.zerosw = 1q <- 1..1wait1sw = 1FTq_next:= q-1TFq <- q_nextq_next = 0TFdb_tick <- 1onesw = 0q <- 1..1wait0sw = 0FTq_next:= q-1TFq <- q_nextq_next = 0TFdb_level <- 1Hardware Design with VHDL FSMs ECE 443ECE UNM 14 (11/19/08)RTL Version of Debouncing CircuitThe signal db_level is the debounced output.The db_tick signal is a one-clock-cycle enable pulse asserted at the zero-to-onetransition, i.e., during the last clock cycle while in state wait1.The zero and one states mean that the sw input has been stabilized for ’0’ and ’1’,respectively.The wait0 and wait1 states filter out short glitches.The datapath consists of one register q which is 21 bits wide.In the zero state, when the sw signal becomes ’1’, the FSMD moves to the wait1 stateand initializes q to all ’1’s.While in wait1, q is decremented by one on each clock cycle as long as swremains ’1’.Once q reaches ’0’, the FSM moves to the one state.With a 50 MHz clock, the delay is 20 ns *


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