Hardware Design with VHDL Synthesis of VHDL Code ECE 443ECE UNM 1 (9/21/09)Synthesis of VHDL CodeThis slide set covers• Fundamental limitation of EDA software• Realization of VHDL operator• Realization of VHDL data type• VHDL synthesis flow• Timing considerationFundamental limitation of EDA softwareCan C-to-hardware be done? No, not reallyEDA tools consist of:• Core: optimization algorithms• Shell: wrappers around the core to carry out conversions, file operations, etc.Theoretical computer science defines• Computability (bounds on what algorithms can do)• Computation complexity (inherent complexity to arrive at an optimal solution)Hardware Design with VHDL Synthesis of VHDL Code ECE 443ECE UNM 2 (9/21/09)Computability and Computational ComplexityA problem is computable if an algorithm existsSome problems are not computable, e.g., the halting problemCan we develop a program that takes any program and its input, and determineswhether the computation of that program will eventually halt?Any attempt to examine the meaning of a program is uncomputableFor computable problems, analysis of computation complexity determines how fastan algorithm can runAlgorithms are analyzed for both time and space complexityComputation time depends on the size of the input, the type of processor, program-ming language, compiler and even coding styleTo eliminate the smaller factors, computational analysis focuses only on the order ofthe algorithm, as a function of the input sizeHardware Design with VHDL Synthesis of VHDL Code ECE 443ECE UNM 3 (9/21/09)Big-O notationf(n) is O(g(n)) if n0 and c can be found to satisfyf(n) < cg(n) for any n, n > n0g(n) is usually a simple function: 1, n, log2n, n2, n3, 2nFor example, the following are O(n2)(0.1n2) <---> (n2 + 5n + 9) <---> (500n2 + 1000000)Interpretation of Big-O• Filter out constants and other less important terms• Focus on scaling factor of an algorithm, i.e., what happens if the input sizeincreasesHardware Design with VHDL Synthesis of VHDL Code ECE 443ECE UNM 4 (9/21/09)Computation complexityIntractable problems are algorithms with O(2n) -- not computable for large nFrequently tractable heuristic algorithms exist, that run in polynomial time, but gen-erate optimal solutions for only some inputs and/or generate sub-optimal solutionsMany problems encountered in synthesis are intractableSynthesis software limitations• Synthesis software cannot obtain the optimal solution• Synthesis should be viewed as a transformation carried out using a local search• Good VHDL code helps a lot by providing a good starting point for the local searchThere are other design tasks that are intractable, and no amount of fast hardware orclever heuristics can be used to find the optimal solutionTherefore, it is impossible for EDA software to completely automate the design pro-cessThis limitation is REAL and is HERE TO STAY!Hardware Design with VHDL Synthesis of VHDL Code ECE 443ECE UNM 5 (9/21/09)Realization of VHDL OperatorsLogic operators: simple, direct mappingRelational operators=, /= fast, simple implementation exists>, <, etc: more complex implementation, larger delayAddition operator, and others that can be derived from addition including subtraction,negation and abs, has a multitude of implementations that trade-off speed and areaEven more complex than the relation operatorsSynthesis support for other operators, e.g., shifting, multiplication, division, expo-nentiation, and floating point operations, is sporadic or non-existentBecause of their complexity, you must be extremely careful about using them inVHDL codeHardware Design with VHDL Synthesis of VHDL Code ECE 443ECE UNM 6 (9/21/09)Realization of VHDL OperatorsOperator with two constant operands: Simplified in preprocessing such that nohardware is inferred -- used because they clarify the codeconstant OFFSET: integer := 8;signal boundary: unsigned(8 downto 0);signal overflow: std_logic;overflow <= ’1’ when boundary > (2**OFFSET-1) else ’0’;Operator with one constant operand: Can significantly reduce (cut-in-half) the hard-ware complexity, e.g., adder vs. incrementer, later implementable with half-addersy <= rotate_right(x, y); -- full-fledged barrel shiftery <= rotate_right(x, 3); -- rewiring, easy to implementy <= x(2 downto 0) & x(7 downto 3); -- rewiringAnother example, 4-bit comparator: x=y vs. x=0Much easier, i.e., only a 4-input NOR gateFull logic expressionHardware Design with VHDL Synthesis of VHDL Code ECE 443ECE UNM 7 (9/21/09)An Example 0.55 um Standard-Cell CMOS ImplementationRealization of VHDL data typeUse and synthesis of ’Z’ and ’-’ (other values other than ’0’ and ’1’ not used insynthesis)’Z’ indicates high impedance (or open circuit)Not a Boolean value but is exhibited in a physical circuit, e.g., as the output of atri-state buffera: optimized foraread: optimized fordelaygate count: inequivalent 2-inputNAND gatesHardware Design with VHDL Synthesis of VHDL Code ECE 443ECE UNM 8 (9/21/09)Tri-State BufferTri-state bufferMajor applications• Bi-directional I/O pins• Tri-state busVHDL descriptiony <= ’Z’ when oe=’1’ else a_in;’Z’ cannot be used as input or manipulatedf <= ’Z’ and a;y <= data_a when in_bus=’Z’ else data_b;oe: output enableHardware Design with VHDL Synthesis of VHDL Code ECE 443ECE UNM 9 (9/21/09)Tri-State BufferBecause a tri-state buffer is not an ordinary logic value, it is a good idea to separate itfrom regular codeLess clear (cannot be synthesized):Better:with sel select y <= ’Z’ when "00", ’1’ when "01"|"11", ’0’ when others;with sel select tmp <= ’1’ when "01"|"11", ’0’ when others; y <= ’Z’ when sel="00" else tmp;Hardware Design with VHDL Synthesis of VHDL Code ECE 443ECE UNM 10 (9/21/09)Bi-directional I/O PinsAn important application of a tri-state bufferentity bi_demo isport(bi: inout std_logic;...begin sig_out <= output_expression;... <= expression_with_sig_in; bi <= sig_out when dir = ’1’ else ’Z’; sig_in <= bi;Hardware Design with VHDL Synthesis of VHDL Code ECE 443ECE UNM 11 (9/21/09)Bi-directional I/O Pins and Tri-State Bussig_in <= bi when dir = ’0’ else ’Z’;Tri-state busAlternative if driving sig_inwith sig_out when dir = ’1’is a problemHardware Design with VHDL Synthesis of VHDL Code ECE 443ECE UNM 12 (9/21/09)Tri-State Buswith src_select select oe <= "0001" when "00", "0010" when "01",