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Hardware Design with VHDL Design Example: VGA ECE 443ECE UNM 1 (11/5/08)VGA (Video Graphics Array)We discuss an 8 color 640-480 pixel resolution interface for the CRT.The electron gun generates a focused electron beam that strikes the phosphor screen.The intensity of the electron beam and the brightness of the dot are determine by thevoltage level of the external video input signal (mono signal).The mono signal is an analog signal whose voltage level is between 0 and 0.7 V.The horizontal and vertical deflection coils produce magnetic fields guid the electronbeam to points on the screen.Electron gunHorizontalosc and amphsyncVerticalosc and ampvsyncHorizontal deflection coilVertical deflection coilElectron beamPhosphorcoatedscreenmonoHardware Design with VHDL Design Example: VGA ECE 443ECE UNM 2 (11/5/08)VGA (Video Graphics Array)The electron beam scans the screen systematically in a fixed pattern.The horz and vert. osc. and amps gen. sawtooth wfms to control the deflection coils.Screenpixel(0,0)h_video_on0retrace(96)639655751799right border (16)640left border (48)’0’ and ’1’ periodsof hsync signalcorrespond to risingand falling rampof sawtooth wfmhsyncHardware Design with VHDL Design Example: VGA ECE 443ECE UNM 3 (11/5/08)VGA (Video Graphics Array)A color CRT is similar except that it has three electron beams, that are projected tothe red, green and blue phosphor dots on the screen.The three dots are combined to form a pixel.The three voltage levels determine the intensity of each and therefore the color.The VGA port has five active signals, hsync, vsync, and three video signals for thered, green and blue beams.They are connected to a 15-pin D-subminiature connector.The video signals are analog signals -- the video controller uses a D-to-A converter toconvert the digital output to the appropriate analog level.If a video is represented by an N-bit word, it can be converted to 2N analog lev-els.Three video signals can generate 23N different colors (called 3N-bit color).If 1-bit is used for each video signals, we get 23 or 8 colors.If all three video signals are driven from the same 1-bit word, we get black&white.Hardware Design with VHDL Design Example: VGA ECE 443ECE UNM 4 (11/5/08)Video ControllerFor the former case:The video controller generates the sync signals and outputs data pixels serially.Red (R) Green (G) Blue (B) Resulting color0 00 black0 01 blue0 10 green0 11 cyan1 00 red1 01 magenta1 10 yellow1 11 whitevga_syncpixel generationcircuithsyncvsyncexternal data/controlpixel_xpixel_yvideo_onrgbVGAmonitorclkHardware Design with VHDL Design Example: VGA ECE 443ECE UNM 5 (11/5/08)Video ControllerThe vga_sync generates the timing and synchronization signals.The hsync and vsync are connected directly to the VGA port.These signals drive internal counters that in turn drive pixel_x and pixel_y.The video_on signal is used to enable and disable the display.pixel_x and pixel_y indicate the relative positions of the scans and essentially specifythe location fo the current pixel.The pixel generator circuit generates three video signals -- the rgb signal.The color value is derived from the external control and data signals.The vga_sync circuit generates the hsync signal, which specifies the time to traverse(scan) a row, while the vsync signal specifies the time to traverse the entire screen.Assume a 640x480 VGA screen with a 25-MHz pixel rate (known as VGA mode).The screen usually includes a small black border around the visible portion.The top-left is coordinate (0, 0) while the bottom right is coordinate (639,479).Hardware Design with VHDL Design Example: VGA ECE 443ECE UNM 6 (11/5/08)Video ControllerOne full period of the hsync signal contains 800 pixels and is divided into 4 regions:• Display: Visible region of screen -- 640 pixels.• Retrace: Region in which the electron beam returns to left edge. Video signal isdisabled and its length is 96 pixels.• Right border: Also known as the front porch (porch before retrace). Video signal isdisabled and its length is 16 pixels (may differ depending on monitor).• Left border: Also known as the back porch. Video signal is disabled and its lengthis 48 pixels (may differ depending on monitor).pixel(0,0)0retrace(96)639655751799right border (16)640left border (48)’0’ and ’1’ periodsof hsync signalcorrespond to risingand falling rampof sawtooth wfmh_video_onhsyncHardware Design with VHDL Design Example: VGA ECE 443ECE UNM 7 (11/5/08)Video ControllerThe hsync signal is obtained by a special mod-800 counter and a decoding circuit.The counter starts from the beginning of the display region.This allows the counter’s output to be used as the x-axis coordinate or pixel_xsignal.The hsync goes low for the counter interval 656 to 751.The h_video_on signal is used to ensure that the monitor is black in the borderregions and during retrace. It is asserted when the counter is smaller than 640.Vertical synchronization:The time unit of the movement is in terms of the horizontal scan lines.One period of the vsync signal is 525 lines, and has a corresponding set of fourregions.0retrace(2 lines)479489491524bottom border (10 lines)480top border (33 lines)v_video_onvsyncHardware Design with VHDL Design Example: VGA ECE 443ECE UNM 8 (11/5/08)Video ControllerA counter is also used here with the output defining the pixel_y coordinate.vsync goes low when line count is 490 or 491.v_video_on is asserted only when line count is less than 480.We assumed the pixel rate was 25 MHz -- this allows 60 screen refreshes/second(anything less results in flicker).s = 60 screens/second * 525 lines/screen * 800 pixels/line = 25.2 Mpixels/sec.HDL ImplementationThe circuit is implemented with two special counters, a mod-800 counter and amod-525 counter.The 50 MHz clock (or 100 MHz clock) is ’divided down’ using an enable tick toenable or pause the counting.This p_tick signal is routed to an output port to coordinate the operation of thepixel generation circuit.Hardware Design with VHDL Design Example: VGA ECE 443ECE UNM 9 (11/5/08)Video Controllerlibrary ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity vga_sync isport(clk, reset: in std_logic;hsync, vsync: out std_logic;video_on, p_tick: out std_logic;pixel_x, pixel_y: out std_logic_vector(9 downto 0));end vga_sync;architecture arch of vga_sync isconstant HD: integer:= 640; -- horizontal displayconstant HF: integer:= 16; -- hsync front porchconstant HB: integer:= 48; -- hsync back


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UNM ECE 443 - ECE 443 Design Example- VGA

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