Hardware Design with VHDL Sequential Circuit Design II ECE 443ECE UNM 1 (9/25/12) Sequential Circuit Design: PracticeTopics• Poor design practice• More counters• Register as fast temporary storage• PipeliningSynchronous design is the most important for designing large, complex systemsIn the past, some non-synchronous design practices were used to save chips/area• Misuse of asynchronous reset• Misuse of gated clock• Misuse of derived clockMisuse of asynchronous reset• Rule: you should never use reset to clear register during normal operationHere’s an example of a poorly designed mod-10 counter which clears the regis-ter immediately after the counter reaches "1010"Hardware Design with VHDL Sequential Circuit Design II ECE 443ECE UNM 2 (9/25/12)Poor Sequential Circuit Design Practicelibrary ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity mod10_counter isport( clk, reset: in std_logic; q: out std_logic_vector(3 downto 0) );end mod10_counter;architecture poor_async_arch of mod10_counter issignal r_reg: unsigned(3 downto 0);signal r_next: unsigned(3 downto 0);signal async_clr: std_logic; beginHardware Design with VHDL Sequential Circuit Design II ECE 443ECE UNM 3 (9/25/12)Poor Sequential Circuit Design Practice -- registerprocess(clk, async_clr)beginif (async_clr = ’1’) then r_reg <= (others => ’0’);elsif (clk’event and clk = ’1’) then r_reg <= r_next;end if;end process;-- asynchronous clearasync_clr <= ’1’ when (reset = ’1’ or r_reg = "1010")else ’0’;-- next state and output logic r_next <= r_reg + 1; q <= std_logic_vector(r_reg);end poor_async_arch;Hardware Design with VHDL Sequential Circuit Design II ECE 443ECE UNM 4 (9/25/12)Poor Sequential Circuit Design PracticeProblem• Transition from "1001" to "0000" goes through "1010" state (see timing diag.)• Any glitches in combo logic driving aync_clr can reset the counter• Can NOT apply timing analysis we did in last chapter to determine max. clk. freq.Asynchronous reset should only be used for power-on initializationHardware Design with VHDL Sequential Circuit Design II ECE 443ECE UNM 5 (9/25/12)Poor Sequential Circuit Design PracticeRemedy: load "0000" synchronously -- looked at this in last chapterarchitecture two_seg_arch of mod10_counter issignal r_reg: unsigned(3 downto 0);signal r_next: unsigned(3 downto 0); begin -- registerprocess(clk, reset)beginif (reset = ’1’) then r_reg <= (others => ’0’);elsif (clk’event and clk = ’1’) then r_reg <= r_next;end if;end process;Hardware Design with VHDL Sequential Circuit Design II ECE 443ECE UNM 6 (9/25/12)Poor Sequential Circuit Design Practice -- next-state logic r_next <= (others => ’0’) when r_reg = 9 else r_reg + 1; -- output logic q <= std_logic_vector(r_reg);end two_seg_arch;Misuse of gated clockRule: you should not insert logic, e.g., an AND gate, to stop the clock fromclocking a new value into a registerHardware Design with VHDL Sequential Circuit Design II ECE 443ECE UNM 7 (9/25/12)Poor Sequential Circuit Design PracticeThe clock tree is a specially designed structure (b/c it needs to drive potentially thou-sands of FFs in the design) and should not be interfered withConsider a counter with an enable signalOne may attempt to implement the enable by AND’ing the clk with itThere are several problems• en does not change with clk, potentially narrowing the actual clk pulse to the FF• If en is not glitch-free, counter may ’count’ more often then it is supposed to• With the AND in the clock path, it interferes with construction and analysis of clockdistribution treeHardware Design with VHDL Sequential Circuit Design II ECE 443ECE UNM 8 (9/25/12)Poor Sequential Circuit Design PracticeA POOR approach to solving this problemlibrary ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity binary_counter isport( clk, reset: in std_logic; en: in std_logic; q: out std_logic_vector(3 downto 0) );end binary_counter;architecture gated_clk_arch of binary_counter issignal r_reg: unsigned(3 downto 0);signal r_next: unsigned(3 downto 0);signal gated_clk: std_logic; beginHardware Design with VHDL Sequential Circuit Design II ECE 443ECE UNM 9 (9/25/12)Poor Sequential Circuit Design Practice -- registerprocess(gated_clk, reset)beginif (reset = ’1’) then r_reg <= (others => ’0’);elsif (gated_clk’event and gated_clk = ’1’) then r_reg <= r_next;end if;end process; -- gated clock -- poor design practice gated_clk <= clk and en; -- next-state and output logic r_next <= r_reg + 1; q <= std_logic_vector(r_reg);end gated_clk_arch;Hardware Design with VHDL Sequential Circuit Design II ECE 443ECE UNM 10 (9/25/12)Poor Sequential Circuit Design PracticeA BETTER approacharchitecture two_seg_arch of binary_counter issignal r_reg: unsigned(3 downto 0);signal r_next: unsigned(3 downto 0); begin -- registerprocess(clk, reset)beginif (reset = ’1’) then r_reg <= (others =>’0’);elsif (clk’event and clk = ’1’) then r_reg <= r_next;end if;end process;Hardware Design with VHDL Sequential Circuit Design II ECE 443ECE UNM 11 (9/25/12)Poor Sequential Circuit Design Practice -- next-state logic r_next <= r_reg + 1 when en = ’1’ else r_reg; -- output logic q <= std_logic_vector(r_reg);end two_seg_arch;Misuse of derived clock• Subsystems may run at different clock rates• Rule: do not use a derived slow clock for the slower subsystemsPoorCorrectHardware Design with VHDL Sequential Circuit Design II ECE 443ECE UNM 12 (9/25/12)Poor Sequential Circuit Design PracticeThe basic problem with the diagram on the left is that the system is no longer syn-chronousThis complicates timing analysis, i.e., we can not use the simple method we looked atearlierWe must treat this as a two clock system with different frequencies and phasesConsider a design that implements a "second and minutes counter"Assume the input clk rate is 1 MHz clockAn example of a POOR design that uses derived clocks is as followslibrary ieee;use ieee.std_logic_1164.cb;PoorCorrectHardware Design with VHDL Sequential Circuit Design II ECE 443ECE UNM 13 (9/25/12)Poor Sequential Circuit Design Practiceuse ieee.numeric_std.all;entity timer isport( clk, reset: in std_logic; sec,min: out std_logic_vector(5 downto 0) );end timer;architecture multi_clock_arch of timer