Hardware Design with VHDL PLDs I ECE 443ECE UNM 1 (9/2/08)PLDs, ASICs and FPGAsFPGA definition:Digital integrated circuit that contains configurable blocks of logic and config-urable interconnects between these blocks.Key points:Manufacturer does NOT determine functionality, rather it is the designer whodefines it after the device is fabricated via programming.FPGAs can be configured at least once, many are reprogrammable.PLDs vs. ASICsPLDs (programmable logic devices): subdivided into SPLDs (simple or justPLDs) and CPLDs (complex).ASICs (application specific integrated circuits): are devices whose functionalityis hardwired, and are not reprogrammable.Hardware Design with VHDL PLDs I ECE 443ECE UNM 2 (9/2/08)PLDs, ASICs and FPGAsPLDs vs. ASICsA PLD’s internal architecture is predetermined by the manufacturer but isdesigned so that it can be configured by engineers in the field.PLDs have a limited number of logic gates (in comparison to FPGAs) and canimplement only simpler logic functions.ASICs offer the ultimate in size, number of transistors, complexity and perfor-mance.However, they are extremely time-consuming and expensive to design.Plus, the design is frozen in silicon, requiring a new version if changes areneeded.FPGAs occupy the middle ground between PLDs and ASICs.They are programmable but contain millions of logic gates, allowing large andcomplex functions to be implemented.Hardware Design with VHDL PLDs I ECE 443ECE UNM 3 (9/2/08)PLDs, ASICs and FPGAsFPGAs vs ASICsThe cost of an FPGA design is much lower than that of an ASIC (given theASIC is not produced in large numbers and cannot amortize this cost).Changing the design is also much easier with an FPGA, and the time-to-marketmuch shorter (than an ASIC).Functions of FPGAs today.Prototype ASIC designs or verify the physical implementation of new algo-rithms.Some include embedded microprocessor cores, high-speed I/O interfaces, andother features.Are used to implement just about anything, including communications devicesand software-defined radios; radar, image and other DSP applications; up tosystem-on-chip (SoC) components.Hardware Design with VHDL PLDs I ECE 443ECE UNM 4 (9/2/08)PLDs, ASICs and FPGAsFPGAs are eating into 4 major market segments:• ASIC and custom silicon• Digital signal processing (DSP)• Embedded microcontrollers• Physical layer communicationsAnd have created a new market themselves• Reconfigurable computingThis refers to exploiting the parallelism and reconfigurability of FPGAs to hard-ware accelerate software algorithms.Applications here span hardware simulation to cryptography.Hardware Design with VHDL PLDs I ECE 443ECE UNM 5 (9/2/08)Fusible Link TechnologiesHow are PLDs and FPGAs programmed?One of the first techniques, fusible-link technology:All of the fuses are initially intact (after manufacturing).Design engineers selectively remove undesired fuses by applying pulses of relativelyhigh voltage and current to the device’s inputs.These devices are one-time programmable, and are not used in FPGAs.&VDDABfusesHardware Design with VHDL PLDs I ECE 443ECE UNM 6 (9/2/08)Antifuse TechnologiesHere, the unprogrammed device has links which are very high in resistance.The compliment of fusible link technology.Connections are selectively grown by applying pulses of relatively high voltage andcurrent to the device’s inputs.Converts highly resistive amorphous silicon to conducting polysilicon.Mask-programmed devicesBasic ROMs (non-volatile read-only memory as opposed to RAM which areread-write and volatile) are mask-programmable.Data in ROMs is hard-coded, using photo-masks that define the metalizationstructure (and connectivity)BLWLVDDMask programmedconnection"weak" pull-up resistorHardware Design with VHDL PLDs I ECE 443ECE UNM 7 (9/2/08)Mask-Programmed DevicesROM can be preconstucted and used to satisfy multiple customers.Customization per customer involves changing a single photo-mask that define whichconnections are present and which are absent.PROMsThe problem with mask-programmable devices:• They are expensive (unless produced in very large quantities).• Are of limited use in development environments, where contents may need to bemodified.Programmable read only memory (PROM) was invented to address these short-comings.BLWLVDDFusible link"weak" pull-up resistorHardware Design with VHDL PLDs I ECE 443ECE UNM 8 (9/2/08)PROMsSimilar to fusible link technology, all fusible links are in place after manufacture.Placing a logic 1 on the word line would cause all column bit lines to pull downto logic 0.Designer blows fuses where he wants logic 1s to be output.These devices were originally intended for use as memories, to store constant pro-grams and data.However, they were also used to implement logic functions, such as lookuptables and state machines.They were cheap and were used to fix bugs and test new implementations.Simply burn a new device and plug it in.Other general-purpose PLDs became available over time (more on this later).Hardware Design with VHDL PLDs I ECE 443ECE UNM 9 (9/2/08)EPROM-based TechnologiesDevices based on fusible link or antifuse could only be programmed a single time.Erasable programmable read-only memory (EPROM) was introduced by Intel in ’71.Accomplished by introducing a floating gate to the basic structure of a MOS transis-tor.When unprogrammed, the floating gate has no effect.toxtoxSourceDrainSubstraten+ n+GateFloating Gate-- - - - - - --5V afterprogrammingthis device off-12V12VHardware Design with VHDL PLDs I ECE 443ECE UNM 10 (9/2/08)EPROM-based TechnologiesProgramming involves placing a high voltage between gate and drain.Hot electrons accumulate on the floating gate, disabling the transistor.Besides being much smaller than fusible links, EPROM cells can be reprogrammed.This is accomplished by discharging the electrons from the floating gate using a UVlight source.Disadvantages: Unprogramming takes about 20 minutes and packages were relativelyexpensive (contained a quartz window).BLWLVDD"weak" pull-up resistorHardware Design with VHDL PLDs I ECE 443ECE UNM 11 (9/2/08)EEPROM-based TechnologiesElectrically erasable programmable read-only memories (EEPROMS) came next.Same basic architecture but now each cell requires two transistors.The upper access transistor was needed because it was not possible to electri-cally remove the electrons from the floating gate in a precise manner.Removing too many left the gate positively charged and always on.Flash memory solved