ECGR-6185µC/OS IINayana RaoUniversity of North Carolina at CharlotteIntroduction and Features• Very small real time OS kernel: OS that enforces timing constraints• Memory footprint is small ~ 20 KB• OS source code is written in C-open source but not free for commercial useMULTITASKING• Process of switching CPU and scheduling between several tasks• Resources are shared• Each task is an infinite loopKERNEL• Responsible for managing tasks and initiate context switching• Pre-emptive kernelSCHEDULING• Preemptive priority driven real time scheduling• 64 priority levels which means maximum allowed tasks = 64• Priority inversion problem: When a task with lower priority holds a resource required by high priority task.Priority Inversion problem:Solution: Priority InheritanceMUTUAL EXCLUSIONAvoidance of simultaneous use of resources• Interrupt Handlers: Enabling and disabling interrupts to manipulate and protect critical sections so that no other ISR or context switch occurs• Semaphores: binary or counting• If Deadlock-> Set timeoutSYNCHRONIZATION AND INTERRUPTS• Between two tasks or between task and ISR• Interrupt informs the CPU of asynchronous events• Interrupt latency is important and should be kept low to improve responsiveness Interrupt latency = max duration for which interrupts are disabled+ time to start executing first instruction in ISRµC/OS II File StructureTasks• Small piece of code that performs some function: infinite loop• Several tasks controlled by a Task Control Block. Also maintains state of task• Task information maintained by OS-Task’s Context• Each task has a unique priority• Each task could be in 1 of 5 states: Dormant, Ready, Running, Waiting, ISRDormant: Procedure residing on RAM/ROM. Not a task till it is called to executeReady: Not delayed or waiting. Contained in a ready listRunning: Task ready or schedule to run on the CPUWaiting: Task is waiting for an event to occur eg: timeout or for semaphore ISR: A task may be per empted by an ISRExample of TaskA task may Delay itself for some clock cyclesClock Ticks• Keeps track of timing and delays• It is an interrupts that is triggered by a timer interruptTask level Scheduling and Context SwitchingScheduler schedules highest priority task to run-Interrupts are disabled during scheduling so that new tasks are not added by other interrupts to the ready listContext Switching (handled at interrupt level) must save CPU registers of the pre-empted task to its stack and be able to restore highest priority task from its taskµC/OS II and the Renesas µC• µC/OS II can be loaded • Initialize and start µC/OS II• Build required
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