SchematicSummaryECE 304: Example Step-Response Design Schematic 0-++-E1GAIN = .50Q_pQ2-7.499mAVPVP+-{V_CC}17.68mA0+R21kOUTSweep+-ACV_AC1V15.00V0VP.model Q_p PNP (Is={I_S} Bf={B_F} Cjc={C_JC} Cje={C_JE} Tf={T_F})+-V2766mVTSF = 1msVSF = .5FIRST_NPAIRS = 0,0, 0.01u,1, 100,1V_PWL_ENH7.499V+{R_S}715.1mVQ_nQ110.18mA0+R17010.10mA+100u14.29V.model Q_n NPN (Is={I_S} Bf={B_F} Cjc={C_JC} Cje={C_JE} Tf={T_F})0INPARAMETERS:R_S = 500V_CC = 15V766.0mVDOT-MODEL PARAMSB_F = 100I_S = 10fAC_JC = 0C_JE = 2pFT_F = 400ps100Meg FIGURE 1 Amplifier made up of a cascade of two CE stages with voltage feedback Time0s10ns20ns30ns40ns50ns60nsV(OUT)2*( V(IN)- V(V2:+))0V1.0V2.0V(1.31n,1.90)(16.7n,1.25)(29.6n,1.08) FIGURE 2 Step response for 0.5V step input; average value is 1V above DC Q-point, as expected for gain with feedback of 1/βFB = 2 V/V Figure 2 shows the uncompensated step response of the amplifier with the DC offsets removed. If the application can tolerate 90% overshoot, this design will work fine with a time to maximum of 1.31 ns. However, if the application can stand only 25% overshoot, the output of this amplifier cannot be used for 16.7 ns, and for 8%, 29.6 ns. That is, the rest of the system has to wait for the amplifier to settle before making use of its output. The system also must tolerate the AC harmonics generated by this oscillatory waveform, or filter them out (which causes delay too). Unpublished material © 4/18/06 J R Brews Page 1 4/18/2006Frequency1.0Hz100Hz10KHz1.0MHz100MHz10GHz1.0THz100THzDB(V(OUT))67.371-20*log10( Frequency/5.5M)-20*log10( Frequency/24.5M)-200-1000(1.0000,67.371) FIGURE 3 Bode gain plot for open loop amplifier fitted to a two-pole model Frequency1.0Hz100Hz10KHz1.0MHz100MHz10GHz1.0THz100THz-atan( Frequency/5.5M)*180/pi-atan( Frequency/24.5M)*180/piVP(OUT)-200-1000 FIGURE 4 Bode phase plot for open-loop amplifier fitted to the same two-pole model Figure 3 shows the Bode gain plot for the open-loop amplifier. It is shown fitted to a two-time constant (that is, two-pole) approximation with frequencies at 5.5 MHz and 24.5 MHz. Figure 4 is the phase plot, fitted to the same two-pole model. The feedback in Figure 1 is implemented with a VCVS. A capacitor insures that the feedback is only AC feedback, so the feedback network doesn’t alter the bias point. A large inductor allows the DC emitter current of the CE stage to reach ground, but blocks the AC feedback signal from reaching ground (we want it to go to the amplifier). For a Butterworth response, a two-pole analysis shows that we need to reduce f1 to f1 = 10.486 kHz, rather than 5.5 MHz. To do this, we need to increase the capacitance of the low frequency node in this circuit. The only capacitors are the two Cπ capacitors, because Cµ has been taken as zero in both transistor dot-model statements (C_JC=0 pF). According to PROBE output file, Cπ for the NPN is 161 pF, and for the PNP is 119 pF. Assuming the time constant CR is proportional to Cπ, one of these Cπ’s must be increased by a factor of 5.5M/10.486k = 524.5. Inspection of the circuit shows that the Cπ for the PNP sees only a low resistance, while that of the NPN sees a much larger resistance. Therefore, we identify the NPN as the capacitor governing the longest time constant. This capacitance must be increased by a factor of 524.5 or to a value of 84.4 nF. This increase is accomplished by placing an external capacitor of 84.3 nF in parallel with Cπ, which means between the base and emitter of the NPN transistor. The amplifier with the compensating capacitor in place is shown in Figure 5. Unpublished material © 4/18/06 J R Brews Page 2 4/18/20060-++-E1GAIN = .50Q_pQ2-7.499mAVPVP+-{V_CC}17.68mA0+R21kOUTSweep+-ACV_AC1V15.00V0VP.model Q_p PNP (Is={I_S} Bf={B_F} Cjc={C_JC} Cje={C_JE} Tf={T_F})+-V2766mVTSF = 1msVSF = .5FIRST_NPAIRS = 0,0, 0.01u,1, 100,1V_PWL_ENH7.499V+{R_S}715.1mVQ_nQ110.18mA0+R17010.10mA+100u14.29V.model Q_n NPN (Is={I_S} Bf={B_F} Cjc={C_JC} Cje={C_JE} Tf={T_F})0INPARAMETERS:R_S = 500V_CC = 15VC_COMP = 84.3nF766.0mV+C2{C_COMP}DOT-MODEL PARAMSB_F = 100I_S = 10fAC_JC = 0C_JE = 2pFT_F = 400ps100Meg FIGURE 5 Compensated amplifier with capacitor C_COMP = 84.3nF placed in parallel with Cπ of the NPN transistor to lower the lowest open-loop pole for the Butterworth step response seen in Figure 6. The step response is now as shown in Figure 6. Time0s 10ns 20ns 30ns 40ns 50ns 60nsV(OUT) 2* (V(IN)-766m)0V1.0V2.0V(C_COMP=0F,1.29n,1.90)(C_COMP=40nF,22.8n,1.22)(C_COMP=84.3nF,38.5n,1.08)(60.0n,1.00) FIGURE 6 Step response with compensating capacitor of CCOMP = 0F, 40nF and 84.3 nF; the DC voltage offsets have been removed In Figure 6 the time to maximum with CCOMP = 84.3 nF is 38.5 ns, which compares well with 40 ns using tMAX ≈ 6.3 τ2 for a Butterworth response. Summary Before compensation, the step response oscillates around the final value, as seen in Figure 6 for CCOMP=0 F. With CCOMP = 84.3 nF, a Butterworth response with 8% overshoot but no significant oscillation results. For a smaller CCOMP = 40 nF, slight oscillation occurs, the time tMAX = 22.8 ns, but the overshoot is 22%. There is a trade-off here between ringing and settling time. An application that can tolerate 22% overshoot can be made faster than one that tolerates only 8% overshoot. Although compensation eliminates ringing, there is a trade-off here between ringing and settling time, and different applications will call for different choices. Unpublished material © 4/18/06 J R Brews Page 3