SchematicAnalysis of polesAmplifier step responseCompensationWhy is the step response of the transistor amplifier so different from its small-signal behavior?Simplified slew-rate simulationECE 304: Compensation of Three-pole System Schematic 0Sweep+-ACVAC1V+100uF-100.00uV-5.000VI1{I_CE}10.05V+-V50100.0uAQ_pQ3-100.0uA-10.00mA+{C_pi1}10.77V0Q_nQ2100.0uA10.00mA+{C_mu2}+{C_mu1}I2{I_T}015.00V0-++-E1GAIN = -0.1+-V4-15V+-V115V+{R_C2}Q_nQ1100.0uA10.00mA+{R_S}+{C_pi2}VPWL_ENHTSF = 1nFIRST_NPAIRS = 0,0, 1,0, 1.001,1 1E20,1VSF = -1.model Q_n NPN (Is=10fA, Bf=100)+{R_C1}9.900mA.model Q_p PNP(Is=10fA, Bf=100)15.00V-714.8mV-15.00VPARAMETERS:C_mu1 = 0.8pFC_mu2 = 0.8pFC_pi1 = 158pFC_pi2 = 158pFI_T = 20.20mAI_CE = 10.1mAR_C1 = 500R_C2 = 1000C_BY = 10_FR_S = 110.05V0+{C_BY}-100.0uVI3{I_T/(2*101)}+{C_mu1}+{C_pi1} VNVPOUT_1VPVPVNOUT_2VNFIGURE 1 Two-stage operational amplifier; zero-voltage source V5 at the output of Stage1 is just a PSPICE convenience to track current into Stage 2 In Figure 1 all the transistor capacitors have been replaced by external capacitances that approximate the Q-point capacitances of the transistors, but do not vary with the applied voltages during a step response. The Bode plots for this amplifier are shown in Figure 3 below. These plots show the amplifier is unstable for unity feedback as f0dB > f180. The minimum value of 1/β for stability is 1/βFB = 19.97 dB, or a maximum βFB of βFB = 0.100 V/V. The step responses for two values of RS and β = 0.1 V/V are shown in Figure 2. The amplifier is unstable for RS > 1 Ω and β = 0.100 V/V. Time0s 1.0ns 2.0ns 3.0ns 4.0nsV(OUT_2) V(0,VAC:-)/0.1-10V0V10V20V30V(R_S=10,12.651)(R_S=1,9.788) FIGURE 2 Small-signal circuit step response for βFB = 0.100 V/V and two values of RS Unpublished work © 4/26/05 J R Brews Page 1 4/27/2005Analysis of poles A simplified analysis neglects the Cµ capacitors of the differential amplifier, which do not contribute much as one end of both is at AC ground. The diff amp transistors are assumed identically biased. All transistors have infinite Early voltages. The CE amplifier contributes two poles and one zero, which are readily assessed following S&S pp. 753-755 and pp. 852-853. The diff amp contributes one pole with time constant Cπ (RS//rπ). The gain expression that results is EQ. 1 ()()µπππµµππππ+ω+ω+ω+ω−ω+−=C)Rg1()r//R(j)r//R(Cj1RCj1R)Cjg()r//R(g)r//R(Cj11R2)r//R(VV2Cm1C1C2C2Cm1CmSSSSO EQ. 1 has a zero in the numerator and a cubic in jω in the denominator. A complete PSPICE simulation is shown in Figure 3 (including all capacitors). Frequency1.0mHz 1.0Hz 1.0KHz 1.0MHz 1.0GHz 1.0THzVDB(OUT_2) VP(OUT_2)+180-300-200-1000100(f_180,1.077G,19.9686)(f_0dB,2.885G,-225.75)(f_180,1.07678G,-180.00)(2.830G,-225.00)(396.70M,-135.00)(1.969M,-45.00)(f_0dB,2.885G,0.00)(10.0000,82.0873) FIGURE 3 Bode magnitude and phase plots for R_S = 1 Ω; amplifier is unstable with phase margin of –225.75+180 = –45.75° and gain margin of –19.97 dB Amplifier step response Using the β-value corresponding to borderline stability (zero phase margin), the step response of the amplifier depends on the height of the step, as shown in Figure 4 below. Unpublished work © 4/26/05 J R Brews Page 2 4/27/2005FIGURE 4 Step response of transistor circuit for different sizes of step: larger steps exhibit slewing The transistor circuit and the small-signal circuit only roughly agree as far as step response is concerned. For example, the transistor circuit shows nonlinear behavior in Figure 4, as evidenced by different waveforms for different step heights. Notice that ringing can be large amplitude, and could drive devices out of the active mode in the transistor circuit, making the small-signal circuit a poor model for step response. Compensation Connecting a capacitor in parallel with Cµ2 of the CE stage, we can lower the corner frequency of the amplifier, making larger β-values possible. The PSPICE Bode plots for several choices of compensation are shown in Figure 5 below. Unpublished work © 4/26/05 J R Brews Page 3 4/27/2005Frequency1.0Hz 100Hz 10KHz 1.0MHz 100MHz 10GHzVDB(OUT_2) VP(OUT_2)+180-400-2000100(1.6917M,Cmu2=1pF)(228.231K,Cmu2=10pF)(f_180,403.122M,-4.2302)(f_0dB,269.488M,-155.534)(f_180,403.122M,-180.000)(770.135M,-225.000)(176.163M,-135.000)(Cmu2=100pF,23.702K,-45.000)(f_0dB,269.488M,0.000)(2.3101K,82.071) FIGURE 5 Compensation using increase of Cµ2 Figure 5 shows the shifting of the corner frequency to lower values to compensate the amplifier. Adding external capacitance in parallel with the parasitic Cµ2 of the PNP CE transistor increases Cµ2. When Cµ2 has increased to 100 pF, the phase margin has become –155.5 –(–180) = 24.5° for unity feedback (βFB = 1 V/V). The gain of this amplifier is 12.7 kV/V, so for a Butterworth response we want f135/f45 = 2 βAo. At Cµ2 = 100 pF, f135/f45 = 176.2M/23.7k= 7.43 k, so the step response is Butterworth if β = 7.43 k/(2 Ao) = 0.293, or 1/β = 10.7 dB. FIGURE 6 Comparison of step-responses for amplifier (top) and its small-signal model (bottom) with Cµ2 = 100 pF Figure 6 shows the step response for the Butterworth value of β = 0.293 V/V. The small-signal model shows tMAX = 6.4ns–1ns = 5.4 ns (the initial delay of 1ns has been subtracted) compared to tMAX = 2π τ135 = 5.7ns, indicating a response close to Butterworth. The transistor amplifier shows a Unpublished work © 4/26/05 J R Brews Page 4 4/27/2005linear rise to final value, characteristic of a constant current charging a capacitor – an indicator of slewing. Why is the step response of the transistor amplifier so different from its small-signal behavior?1 Instead of rising quickly to its final value, the amplifier response follows a slow linear ascent to its final value. This behavior is an example of slew-rate limitations. That is, the amplifier cannot supply enough current to drive the capacitances in the system when the voltage step is large. We estimate how long it takes to swing the final output voltage up by 1.7V as follows: 1. Initially the output is at –5V, placing about 15V across capacitor Cµ2. For the voltage across Cµ2 to decrease by 1.7 V, current not only must be supplied by the PNP transistor Q3, but this current must be sunk by Stage 1. 2. The voltage across collector resistor RC1 at the Q-point is set to balance Stage 1 using the base current supplied by I3. Let’s suppose that this voltage doesn’t change