SchematicHow does it work?Design goalAC and DC beta-valuesThe Q_pVAF dot-model parametersEarly voltage: parameter VAFBase resistance: parameter Rb and the intrinsic base resistance rXCurrent dependence of small-signal parameters; parameter ?Setting ?Hand analysisQ-point analysisSmall-signal analysisTransient analysisSpreadsheetVerification of spreadsheetQ-point verificationSmall-signal verificationTransient behaviorComparison with a more realistic transistor modelUsing the spreadsheet as a design toolTrend of RN with mid-base voltage VM when IC = constantTrend of RN with output current IC when VM = constantTrend of RR and RE with VM when IC = constantTrend of RR and RE with IC when VM = constantExample designCommentsAppendix: the diode-connected transistorExercisesSoftware elements presentedCapture and PSpiceExcelPNP current mirror Schematic +-{V_CC}20.089mAPARAMETERS:V_CC = 10VR_E = 418.85833R_R = 495.59372V_SAT = 0.55V5.7928V5.0000V-++-E1GAIN = 105.0000VSweep+-ACV_ac1V0+{R_R}10.089mA.model Q_pVAF PNP (Bf={B_F} Is={I_S} Vaf={V_AF}Nf={N_F} Rb={r_X})5.7928V+{R_E}10.044mAQ_pVAFQ_Ref-44.455uA-10.000mADOT -MODEL:B_F = 224.9477I_S = .6506fAV_AF = 115.7VN_F = 1.0089535r_X = 10+-{V_A}V_DC+{R_E}10.044mAINPUT SIGNALAMPLITUDE = 1VV_A = 5FREQUENCY = 1kHz0-+Transient Analysis{AMPLITUDE}{FREQUENCY}V_SIN792.80mV10.000V05.0000VQ_pVAFQ_Out-44.455uA-10.000mA5.0000V OUTMEEEMMFigure 1 Figure 1Circuit for pnp current mirror using simple device with dot-model statement shown Figure 1 shows a schematic for a pnp current mirror.1 The purpose of the mirror is to emulate an ideal current source, that is, to provide the same DC current through the output node regardless of the voltage applied, DC or transient. How does it work? The basic idea behind the circuit is that the left side draws a current through the reference transistor setting up a corresponding emitter-base voltage. Because the circuit is 1 Also shown in is an evaluator circuit using PSPICE VCVS Part E just to display the value of VEM on the schematic for easy comparison with the spreadsheet constructed in this chapter. Unpublished work © 2006 by John R Brews 1symmetric (assuming the output and reference transistors are alike) the same VEB appears at the output transistor, so the same current flows there (it is mirrored), almost independent of the voltage VA because VA hardly affects VEB. Unfortunately, the mirror is not entirely successful, having these limitations: 1. It provides a nearly constant DC current only over a limited range of voltages. This limitation arises at voltages VA > VM (VM = mid-base voltage), where the output transistor QOut leaves active mode and goes into saturation. 2. Even in the range of voltages VA < VM where QOut is active, the current is not strictly constant, but varies somewhat with VA. That is, the circuit resembles a Norton source with a finite Norton resistance instead of an ideal current source. This limitation is due to the finite output resistance of transistor QOut. The above limitations are illustrated in Figure 2. VSAT Active Mode VCVFigure 2 Circuit output behavior for Figure 1; at the compliance voltage VCV where output resistance begins a rapid drop to low values, the output transistor is in saturation by VBC = −VSAT The top panel in Figure 2 shows the current-voltage I-V behavior of the mirror. It delivers a DC current of 10 mA for voltages below approximately 5.55V. The lower panel shows the resistance of the mirror, determined as the inverse of the derivative of the current by voltage. It shows that this resistance is high (934 kΩ at VA = 1 V), but not quite constant, and drops suddenly just above VA = VM = 5 V. The drop-off voltage is called the compliance voltage VCV of the mirror, and the voltage range where nearly Unpublished work © 2006 by John R Brews 2constant DC current is delivered is the compliance range of the mirror. If we choose the bias at 3 dB roll-off of resistance as the verge of the drop, we find the compliance voltage is VCV = 5.346 V from Figure 2. At this bias, the output transistor is in saturation by an amount VBC = −VSAT = −0.346 V. At the point where the DC current has just begun to drop (VA = 5.55 V) the output resistance of the mirror already is at a very low value of only 9.34 kΩ, showing that the Norton resistance of the mirror is much more sensitive to saturation of the output transistor than is the DC current itself. Because the limitations of the mirror depend on the limitations of the transistor, we need a transistor model that includes the Early voltage of the device. Otherwise, the mirror would still have a voltage limitation, but would be an ideal current source as long as QOut was active. Hence, we have the dot-model statement in Figure 1, discussed in detail shortly. Design goal We want to design the circuit of Figure 1 to meet specifications on DC current level IC at VA = VM (both transistors with VBC = 0 V), on compliance voltage VCV (taken as a specification on VM because VM is unambiguous and differs from VCV by only the small voltage VSAT discussed later2), and specifications on output resistance RN (Norton resistance) of the mirror. The variables at our disposal are the leg resistor value RE and the reference resistor value RR, so unless we are lucky only two of the three specifications can be satisfied, and a trade-off will be necessary. For this purpose we will set up a spreadsheet incorporating the hand analysis below. AC and DC beta-values For the dot-model statement of Figure 1, the small-signal AC β-value, which will be called βAC, is the same as the DC β-value, which is called βDC. However, that is not so for more complex models, so we include this difference in the equations here. EQ. 1 defines DC β: 2 The value of VSAT is expected to be somewhere around 0.5 V, but its value is unknown without a simulation. It varies with the type of transistor and with the current and bias conditions. Unpublished work © 2006 by John R Brews 3EQ. 1 BICIDC=β, while AC β is defined by: EQ. 2 ()CdIDCdDCCIDCCdIDCdDCCIDCDCCIdCdIBdICdIACββββββββ−=−===1211/. According to EQ. 2, βAC is different from βDC if βDC depends on IC. For the dot-model statement of Figure 1 βDC does not depend on IC, but for real transistors it does. So, for real transistors, βDC and βAC are the same only at the maximum in the βDC vs. IC curve. An example is shown in Figure 3 below. IE10nA 1.0uA 100uA 10mA 1.0AI(C)/I(B) D(I(C))/