PowerPoint PresentationCombinational-Circuit AnalysisCombinational-Circuit DesignAlarm-circuit transformationSum-of-products formProduct-of-sums formBrute-force designMinterm list --> canonical sumAlgebraic simplificationResulting circuitVisualizing T10 -- Karnaugh maps3-variable Karnaugh mapExample: F = S(1,2,5,7)Karnaugh-map usagePrime-number detector (again)Slide 16Another exampleYet another examplePOSSlide 20In-Class Practice ProblemSlide 22Quine-McCluskey algorithmLots of possibilitiesReal-World Logic DesignVHDLVHDL TopicsSlide 28ObjectivesVHDL HistoryApplication Areas for VHDLVHDL Design UnitEntity DescriptionModeling InterfacesVHDL-87Architecture DescriptionPackage and Package BodyConfigurationA Range of Design ExamplesLevels of AbstractionArchitecture TypesModeling BehaviorBehavior ExampleSlide 44Modeling StructureStructural ArchitectureSlide 47Slide 48Structure ExampleSlide 50Slide 51Slide 52Slide 53Mixed Behavior and StructureSlide 55Slide 56Slide 57Slide 58Slide 59Slide 60Test BenchesTest Bench ExampleRegression TestingDesign ProcessingAnalysisElaborationElaboration ExampleSlide 68SimulationSimulation AlgorithmSlide 71SynthesisBasic Design MethodologyHow we’ll SimulateMore VHDL HelpNext timeEE365Adv. Digital Circuit DesignClarkson UniversityLecture #3Combinational LogicCombinational-Circuit Analysis•Combinational circuits -- outputs depend only on current inputs (not on history).•Kinds of combinational analysis:–exhaustive (truth table)–algebraic (expressions)–simulation / test bench (example in lab #2)•Write functional description in HDL•Define test conditions / test vecors, including corner cases•Compare circuit output with functional description (or known-good realization)•Repeat for “random” test vectorsRissacher EE365Lect #3Combinational-Circuit Design•Sometimes you can write an equation or equations directly using “logic” (the kind in your brain).•Example (alarm circuit):•Corresponding circuit:Rissacher EE365Lect #3Alarm-circuit transformation•Sum-of-products form–Useful for programmable logic devices (next lec.)•“Multiply out”:Rissacher EE365Lect #3Sum-of-products formAND-ORNAND-NANDRissacher EE365Lect #3Product-of-sums formOR-ANDNOR-NORP-of-S preferred in CMOS, TTL (NAND-NAND)Rissacher EE365Lect #3Brute-force design•Truth table --> canonical sum (sum of minterms)•Example:prime-number detector–4-bit input, N3N2N1N0row N3 N2 N1 N0 F 0 0 0 0 0 0 1 0 0 0 1 1 2 0 0 1 0 1 3 0 0 1 1 1 4 0 1 0 0 0 5 0 1 0 1 1 6 0 1 1 0 0 7 0 1 1 1 1 8 1 0 0 0 0 9 1 0 0 1 010 1 0 1 0 011 0 0 1 1 112 1 1 0 0 013 1 1 0 1 114 1 1 1 0 015 1 1 1 1 0F =       (1,2,3,5,7,11,13)Rissacher EE365Lect #3Minterm list --> canonical sumRissacher EE365Lect #3Algebraic simplification•Theorem T8, •Reduce number of gates and gate inputsRissacher EE365Lect #3Resulting circuitRissacher EE365Lect #3Visualizing T10 -- Karnaugh mapsRissacher EE365Lect #33-variable Karnaugh mapRissacher EE365Lect #3Example: F =  (1,2,5,7)Rissacher EE365Lect #3Karnaugh-map usage•Plot 1s corresponding to minterms of function.•Circle largest possible rectangular sets of 1s.–# of 1s in set must be power of 2–OK to cross edges•Read off product terms, one per circled set.–Variable is 1 ==> include variable–Variable is 0 ==> include complement of variable–Variable is both 0 and 1 ==> variable not included•Circled sets and corresponding product terms are called “prime implicants”•Minimum number of gates and gate inputsRissacher EE365Lect #3Prime-number detector (again)Rissacher EE365Lect #3Prime-number detector (again)•When we solved algebraically, we missed one simplification -- the circuit below has three less gate inputs.Rissacher EE365Lect #3Another exampleRissacher EE365Lect #3Yet another example•Distinguished 1 cells•Essential prime implicantsRissacher EE365Lect #3POS•Circle ‘0’s•Use DeMorgans to invert the equation Rissacher EE365Lect #3F’ = (W’•Y•X)+(X’•Z’)F = ((W’•Y•X)+(X’•Z’))’F = (W’•Y•X)’•(X’•Z’)’F = (W+Y’+X’)•(X+Z)POSRissacher EE365Lect #3•Note that the textbook author likes to draw the Karnaugh map for the F’ function, thus you would circle the ‘1’s (where my examples show the F function and ‘0’s are cirlced).In-Class Practice ProblemRissacher EE365Lect #3Using Karnaugh maps, find the minimal SOP and POS terms for:F=ΣW,X,Y,Z(0,2,5,7,8,10,13,15)In-Class Practice ProblemRissacher EE365Lect #3SOP:POS:Z • X’X • Z’Quine-McCluskey algorithm•This process can be made into a program, using appropriate algorithms and data structures.–Guaranteed to find “minimal” solution•Required computation has exponential complexity (run time and storage)-- works well for functions with up to 8-12 variables, but quickly blows up for larger problems.•Heuristic programs (e.g., Espresso) used for larger problems, usually give minimal results.Rissacher EE365Lect #3Lots of possibilities•Can follow a “dual” procedure to find minimal products of sums (OR-AND realization)•Can modify procedure to handle don’t-care input combinations.•Can draw Karnaugh maps with up to six variables.Rissacher EE365Lect #3Real-World Logic Design•Some applications have lots more than 6 inputs–can’t use Karnaugh maps•Design correctness more important than gate minimization–Use “higher-level language” to specify logic operations•Use programs to manipulate logic expressions and minimize logic.•PALASM, ABEL, CUPL -- developed for PLDs•VHDL, Verilog -- developed for ASICsRissacher EE365Lect #3VHDL•We will be using VHDL for all design projects•We generally won’t be using VHDL to help with minimization, rather as a method to simulate simple logic circuits built with MSI components•The following slides will cover the basic syntax of using VHDL for our purposes•Program usage (e.g., Xilinx Modelsim) and program/circuit testing will be covered in a separate tutorialRissacher EE365Lect #3VHDL Topics•Objectives•VHDL History•Application Areas•Design Units•Entity Descriptions•Architecture Descriptions•Package and Package Body•Configuration•A Range of Design ExamplesRissacher EE365Lect #3VHDL Topics•Levels