EE365 Adv Digital Circuit Design Clarkson University Lecture 14 CPLDs FPGAs Topics CPLDs FPGAs Lect 14 Rissacher EE365 PLDs 16V8 20 Pins can have 16 inputs max and or 8 outputs marcrocells has 32 inputs to each of the AND gates product terms 22V10 24 pins can have 22 inputs and or 10 outputs max has 44 inputs to each of the AND gates How about a 128V64 for larger applications It will be slower and will more wasted silicon space Lect 14 Solution Use CPLDs Rissacher EE365 The TheOR ORgates gates GAL16V8 review seq 1 ppt Each output is programmable as combinational or registered Also has programmable output polarity Lect 14 And AndPlane Plane XOR XORgates gatesto to make makeinverting invertingor or non inverting non invertingbuffer buffer Rissacher EE365 A General CPLD structure A collection of PLDs on a single chip with Programmble interconnects Lect 14 Rissacher EE365 Who makes the CPLDs Manufacturer Manufacturer Altera Altera Altmel Altmel Cypress Cypress Lattice Lattice Philips Philips Vantis Vantis Xilinx Xilinx CPLD CPLDProducts Products MAX MAX5000 5000 7000 7000 9000 9000 ATF ATF ATV ATV FLASH370 FLASH370 Ultra37000 Ultra37000 ispLSI ispLSI1000 1000toto8000 8000 XPLA XPLA MACH MACH11toto55 XC9500 XC9500 URL URL www altera com www altera com www atmel com www atmel com www cypress com www cypress com www latticesemi com www latticesemi com www philips com www philips com www vantis com www vantis com www xilinx com www xilinx com Let s Let stakes takesaalook lookatatthis this Lect 14 Rissacher EE365 The Xilinx 9500 series CPLD The internal PLDs are called Configurable Functional Blocks FBs or CFBs Each FB has 36 inputs and 18 Macrocells effectively a 36V18 Each CLPD is packaged in a plastic leaded chip carrier PLCC The number of I O pins are much less than the total number of Macrocells in family of devices Lect 14 Rissacher EE365 Xinlinx CPLDs Lect 14 Rissacher EE365 Architecture of Xilinx 9500 family CPLD 36 36Signal Signalpins pins 18 18outputs outputs Global GlobalClock Clock Lect 14 Global Globalset reset set reset Global Global33state statecontrol control 18 18Output Output enable enablesignals signals Rissacher EE365 Architecture of Xilinx FB Most CLPDs have fewer AND terms per macrocell XC9500 has 5 whereas 16V8 has 8 and 22V10 has 8 16 But each macrocell can use unused ANDs from its neighboring macrocells using the product term allocators Lect 14 Rissacher EE365 Lect 14 XC9500 XC9500Product Product term termallocator allocatorand and macrocell macrocell Rissacher EE365 ISP ISP Lect 14 Rissacher EE365 Lect 14 Rissacher EE365 XC9500 XC9500I O I OBlock Block Lect 14 Rissacher EE365 Lect 14 Rissacher EE365 Switch matrix for XC95108 Could be anything from a limited set of multiplexers to a full crossbar Multiplexer small fast but difficult fitting Crossbar easy fitting but large and slow 1 Lect 14 Rissacher EE365 XC4000E I O Block Lect 14 Rissacher EE365 FPGAs Historically FPGA architectures and companies began around the same time as CPLDs FPGAs are closer to programmable ASICs large emphasis on interconnection routing Timing is difficult to predict multiple hops vs the fixed delay of a CPLD s switch matrix But more scalable to large sizes FPGA programmable logic blocks have only a few inputs and 1 or 2 flip flops but there are a lot more of them compared to the number of macrocells in a CPLD Lect 14 Rissacher EE365 General FPGA chip architecture a k a CLB configurable logic block Lect 14 Rissacher EE365 Xilinx 4000 series FPGAs Lect 14 Rissacher EE365 FPGA specsmanship Two flip flops per CLB plus two per I O cell 25 gates per CLB if used for logic 32 bits of RAM per CLB if not used for logic All of this is valid only if your design has a perfect fit Lect 14 Rissacher EE365 Configurable Logic Block CLB Lect 14 Rissacher EE365 CLB function generators F G H Use RAM to store a truth table F G 4 inputs 16 bits of RAM each H 3 inputs 8 bits of RAM RAM is loaded from an external PROM at system initialization Broad capability using F G and H Lect 14 Any 2 funcs of 4 vars plus a func of 3 vars Any func of 5 vars Any func of 4 vars plus some funcs of 6 vars Some funcs of 9 vars including parity and 4 bit cascadable equality checking Rissacher EE365 CLB input and output connections buried in the sea of interconnect Lect 14 Rissacher EE365 Detail connections controlled by RAM bits Lect 14 Rissacher EE365 Programmable Switch Matrix programmable switch element turning the corner etc Lect 14 Rissacher EE365 The fitter s job Partition logic functions into CLBs Arrange the CLBs Interconnect the CLBs Minimize the number of CLBs used Minimize the size and delay of interconnect used Work with constraints Locked I O pins Critical path delays Setup and hold times of storage elements Lect 14 Rissacher EE365 Oh by the way I O blocks Lect 14 Rissacher EE365 Problems common to CPLDs and FPGAs Pin locking Small changes and certainly large ones can cause the fitter to pick a different allocation of I O blocks and pinout Locking too early may make the resulting circuit slower or not fit at all Running out of resources Design may blow up if it doesn t all fit on a single device On chip interconnect resources are much richer than offchip e g barrel shifter example Larger devices are exponentially more expensive Lect 14 Rissacher EE365 Next time SRAM DRAM Lect 14 Rissacher EE365