PowerPoint PresentationTopicsSerial data systems (e.g., TPC)Serial data in the phone system (E-1)Timeslot detailsParallel-to-serial conversionSerial-to-parallel conversionDestination timingSerial communication on ONE wireStill a couple of problemsSynchronous System StructureTypical synchronous-system timingClock SkewClock-skew calculationIn-Class Practice ProblemSlide 16Slide 17Slide 18Example of bad clock distributionClock distribution in ASICs“Clock-tree” solutionGating the clockIf you really must gate the clock...Asynchronous inputsA simple synchronizerOnly one synchronizer per inputEven worseThe way to do itRecommended synchronizer designMetastability decision windowMetastability resolution timeFlip-flop metastable behaviorTypical flip-flop metastability parametersIs 1000 years enough?Multiple-cycle synchronizerDe-skewed multiple-cycle synchronizerNext timeEE365Adv. Digital Circuit DesignClarkson UniversityLecture #13Clock Skew & SynchronizationTopicsRissacher EE365Lect #13•More Serial•Clock Skew•SynchronizationSerial data systems (e.g., TPC)Rissacher EE365Lect #13Serial data in the phone system (E-1) •2.048 Mb/s links between phone switches and subscribers–partitioned into 32 64 Kb/s channels•Each channel gets a timeslot in a “frame” where it can send 8 bits every 125 sec.–8000 frames/secRissacher EE365Lect #13Timeslot detailscount = 255Rissacher EE365Lect #13Parallel-to-serial conversion256LSBs are bit numberAssert shift-registerLOAD input during bit 7Timeslot number canbe decoded and usedto select source ofparallel dataSerial data todestinationcount = 255Rissacher EE365Lect #13Serial-to-parallel conversionSynchronize destination’s counter to source’sShift in serial dataDetect that acomplete bytehas beenreceivedHolding registerfor completebyteNote:loads0…0Rissacher EE365Lect #13Destination timingSerial-in, parallel-outshift register outputsHolding-register outputsGrab complete byte when availableRissacher EE365Lect #13Serial communication on ONE wire•Serial communication requires three signals: CLOCK, SYNC, and DATA. Yet only one “wire” is used. How?•One solution: Manchester code.•Or use a phase-locked loop (analog circuit)to extract clock from the data:Rissacher EE365Lect #13Still a couple of problems•Framing -- SYNC signal–Solution: Use a unique data pattern for SYNC•PLL clock recovery -- what if too many zeroes are transmitted? PLL can’t stay in sync.–Solution: Use a code that guarantees a minimum number of ones–Phone system: Map 00000000 --> 00000010 (creating slight voice distortion)•Gigabit Ethernet: Uses 8B10B code, solving both problems–Map each byte into 8 bits–Use only a “good” subset of 210 code words–Use another code word for synchronizationRissacher EE365Lect #13Synchronous System StructureEverything is clocked by the same, common clockRissacher EE365Lect #13Typical synchronous-system timing•Outputs have one complete clock period to propagate to inputs.•Must take into account flip-flop setup times at next clock period. Rissacher EE365Lect #13Clock Skew–Clock signal may not reach all flip-flops simultaneously.–Output changes of flip-flops receiving “early” clock may reach D inputs of flip-flops with “late” clock too soon.Reasons for slowness:(a) wiring delays(b) capacitance(c) incorrect designRissacher EE365Lect #13Clock-skew calculation•tffpd(min) + tcomb(min)  thold  tskew(max) > 0•First two terms are minimum time after clock edge that a D input changes•Hold time is earliest time that the input may change•Clock skew subtracts from the available hold-time margin•Compensating for clock skew:–Longer flip-flop propagation delay–Explicit combinational delays–Shorter (even negative) flip-flop hold timesRissacher EE365Lect #13In-Class Practice ProblemRissacher EE365Lect #13tffpd(min) = 5 nstcomb(min) = 20 nsthold = 20 ns tskew(max) = 10 nsComb Logic(Excitation Eqns)CLKDelayCalculate whether clock-skew is an issue for the indicated Flip-FlopIn-Class Practice ProblemRissacher EE365Lect #13tffpd(min) = 5 nstcomb(min) = 20 nsthold = 20 ns tskew(max) = 10 nstffpd(min) + tcomb(min)  thold  tskew(max) = -5 nsCalculate whether clock-skew is an issue for the indicated Flip-FlopIn-Class Practice ProblemRissacher EE365Lect #13tffpd(min) = 5 nstcomb(min) = 20 nsthold = 20 ns tskew(max) = 10 nsComb Logic(Excitation Eqns)CLKDelayNow add a delay to the circuit to fix the issue.In-Class Practice ProblemRissacher EE365Lect #13tffpd(min) = 5 nstcomb(min) = 20 nsthold = 20 ns tskew(max) = 10 nsComb Logic(Excitation Eqns)CLKDelay> 5 nsExample of bad clock distributionRissacher EE365Lect #13Clock distribution in ASICs•This is what a typical ASIC router will do if you don’t lay out the clock by hand.Rissacher EE365Lect #13“Clock-tree” solution•Often laid out by hand•Wide,fast metal (low R ==> fast RC time constant)Rissacher EE365Lect #13Gating the clock•Definitely a no-no–Glitches possible if control signal (CLKEN) is generated by the same clock–Excessive clock skew in any case.Rissacher EE365Lect #13If you really must gate the clock...Rissacher EE365Lect #13Asynchronous inputs•Not all inputs are synchronized with the clock•Examples:–Keystrokes–Sensor inputs–Data received from a network (transmitter has its own clock)•Inputs must be synchronized with the system clock before being applied to a synchronous system.Rissacher EE365Lect #13A simple synchronizerRissacher EE365Lect #13Only one synchronizer per inputRissacher EE365Lect #13Even worse•Combinational delays to the two synchronizers are likely to be different.Rissacher EE365Lect #13The way to do it•One synchronizer per input•Carefully locate the synchronization points in a system.•But still a problem -- the synchronizer output may become metastable when setup and hold time are not met.Rissacher EE365Lect #13Recommended synchronizer design•Hope that FF1 settles down before “META” is sampled.–In this case, “SYNCIN” is valid for almost a full clock period.–Can calculate the probability of “synchronizer failure” (FF1 still metastable when META sampled)Rissacher EE365Lect #13Metastability decision windowRissacher EE365Lect #13Metastability resolution timeRissacher EE365Lect #13Flip-flop metastable behavior•Probability of flip-flop output being in the metastable state is an exponentially decreasing function of tr (time since clock edge, a.k.a. “resolution