PowerPoint PresentationSlide 2Slide 3Slide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 12Slide 13Slide 14Slide 15Slide 16Slide 17Slide 18Slide 19Slide 20Slide 21Slide 22Slide 23Slide 24Slide 25Slide 26Slide 27Slide 28Slide 29EE365Adv. Digital Circuit DesignClarkson UniversityLecture #1Course OutlineNumber Systems• No mid-course exams (only final exam)• Design Problems heavily weighted• Optional homeworks• Quizzes (every few days) correspond to HWs• Textbook: does everyone have it?• Office Hours: where/when• Contact information (phone, e-mail, AIM)Rissacher EE365SyllabusLect #1www.clarkson.edu/class/ee365• Schedule• Notes (suggest printing before class)• Handouts• Class Location (some will be in computer lab)• LinksRissacher EE365Course WebsiteLect #1• Interrupt me at anytime for questions• Discussions encouraged• Grade not based on attendance• Feel free to excuse yourself at any time (e.g., if you’re falling asleep go stretch your legs and buy a mountain dew, or leave after quiz is over)• Bring scrap paper: I may give in-class practice problemsRissacher EE365Lecture StructureLect #1• Heavily weighted• May take some time, start early & use the weekends• Will have at least one in-class help session for each project.• Each project will require you to hand in files on floppy or CD (your choice)… make sure you have a supply before the first project is dueRissacher EE365ProjectsLect #1General Topics:• Basic Logic Review• Logic Laws/Theorems/Methods• VHDL• Transistor-Level Logic Implementation• Electrical Behavior (timing, hazards, etc.)• MSI Devices (Gates, Encoders, MUXs, registers, etc.)• Sequential Logic• LSI/VLSI Devices (memory, CPLDs, FPGAs)Rissacher EE365OverviewLect #1Will be covered later todayRissacher EE365Number Systems & MathLect #1• DeMorgan’s Law, Sum of Products, Product of Sums• Minterm, Maxterm• Karnaugh Maps• Commutativity, Associativity, etc.Rissacher EE365Logic Laws & MethodsLect #1Rissacher EE365VHDLLect #1entity and2 isport ( a, b : in bit; y : out bit );end and2;architecture basic of and2 isbeginand2_behavior : processbeginy <= a and b after 2 ns;wait on a, b;end process and2_behavior;end basic;Rissacher EE365Transistor-Level Logic ImplementationLect #1Rissacher EE365Electrical BehaviorLect #1• Propagation Delay• Fan-In, Fan-Out• Timing Hazards• etcRissacher EE365MSI DevicesLect #174x541D0 Y0...D7 Y7G1G274x541D0 Y0...D7 Y7G1G274x541D0 Y0...D7 Y7G1G274x541D0 Y0...D7 Y7G1G28G Y0 Y1A Y2B Y31/2 of74x139A0A1data 0data 3data 2data 1Encoders, Decoders, Multiplexers, Registers, PLDs, Comparators, Adders, Subtractors, ALUs, etc.Rissacher EE365Sequential LogicLect #1Rissacher EE365LSI/VLSI DevicesLect #1• ROMs• SRAM• DRAM• CPLDs• FPGAsRissacher EE365Lect #1Number Systems• Binary• Hex• Octal• Addition/Subtraction•Negative NumbersRissacher EE365Lect #1Number Systems2n10n8n16nWhere n is the bit #, or decimal placeRissacher EE365Lect #1Binary AdditionRissacher EE365Lect #1Binary SubtractionRissacher EE365Lect #1Negative Binary Numbers• Signed-Magnitude• Two’s ComplementRissacher EE365Lect #1Signed-Magnitude• MSB represents the sign• Other bits represent the value• 01010101 = +85• 11010101 = -85Rissacher EE365Lect #1Two’s Complement• MSB represents the sign• Other bits represent the value if positive• Complement + 1 of other bits represents the value if negative• creates a continuous number line so that if we start with most negative number and count up, we see that each successive number can be obtained• e.g., 17 = 00010001, complement = 11101110 + 1 = 11101111 = -17Rissacher EE365Lect #1Two’s Complement Addition/Subtraction +3 0011+ +4 0100 +7 0111 +4 0100+ -7 1001 -3 1101• Ignore carry bits into MSB• For subtraction, simply negate one of the numbersRissacher EE365Lect #1Binary Multiplication/Division• Very similar to the multiplication and long division methods that we learned in elementary schoolRissacher EE365Lect #1Binary Multiplication• Multiplication is achieved by adding a list of shifted multiplicands according to the digits of the multiplier• Un-signed example:Rissacher EE365Lect #1Binary Multiplication• Instead of listing all shifted multiplicands before adding, we can add each shifted multiplicand to a partial product (move convenient in a digital system):Rissacher EE365Lect #1Two’s Complement Multiplication• A sequence of two’s-complement additions is similar except for the last step where the shifted multiplicand (corresponding to the MSB) must be negated:Rissacher EE365Lect #1Binary Division• Use long division, shift and subtract (shown below)• Direct two’s complement method not discussed here, but sign can be handled by negating the quotient if the dividend and divisor had different signsRissacher EE365Lect #1Next Time• Logic Theorems• Sum-of-Products vs. Product-of-Sums• Minterms/Maxterms• Logic Function RepresentationsRissacher EE365Lect #1Homework• E-mail me your contact information and preferred methods of reaching you• Please include e-mail, phone, messenger names, etc.• my address: