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PowerPoint PresentationTopicsSequential CircuitsDescribing Sequential CircuitsSlide 5Clock signalsBistable elementSlide 8Analog analysisSlide 10Slide 11MetastabilityAnother look at metastability“sube y baja” behaviorWhy all the harping on metastability?Back to the bistable….S-R latch operationS-R latch timing parametersS-R latch symbolsS-R latch using NAND gatesS-R latch with enableD latchD-latch operationD-latch timing parametersEdge-triggered D flip-flop behaviorD flip-flop timing parametersTTL edge-triggered D circuitCMOS edge-triggered D circuitOther D flip-flop variationsScan flip-flops -- for testingJ-K flip-flopsT flip-flopsIn Class Practice ProblemSlide 34In Class Practice Problem #2Slide 36Slide 37Slide 38Sequential PALsOne output of 16R8PAL16R6GAL16V8GAL16V8 output logic macrocellGAL22V10GAL22V10 output logic macrocellNext timeEE365Adv. Digital Circuit DesignClarkson UniversityLecture #10Latches, Flip Flops & Sequential PALSTopics•Basic Definitions•Latches•Edge-Triggered Flip-Flops•Timing RequirementsRissacher EE365Lect #10Sequential Circuits•Output depends on current input and past history of inputs.•“State” embodies all the information about the past needed to predict current output based on current input.–State variables, one or more bits of information.Rissacher EE365Lect #10Describing Sequential Circuits•State table–For each current-state, specify next-states as function of inputs–For each current-state, specify outputs as function of inputsRissacher EE365Lect #10Describing Sequential Circuits•State diagram–Graphical version of state tableRissacher EE365Lect #10Clock signals•Very important with most sequential circuits–State variables change state at clock edge.Rissacher EE365Lect #10Bistable element•The simplest sequential circuit•Two states–One state variable, say, QHIGH LOWLOW HIGHRissacher EE365Lect #10Bistable element•The simplest sequential circuit•Two states–One state variable, say, QLOW HIGHHIGH LOWRissacher EE365Lect #10Analog analysis•Assume pure CMOS thresholds, 5V rail•Theoretical threshold center is 2.5 VRissacher EE365Lect #10Analog analysis•Assume pure CMOS thresholds, 5V rail•Theoretical threshold center is 2.5 V2.5 V 2.5 V2.5 V 2.5 VRissacher EE365Lect #10Analog analysis•Assume pure CMOS thresholds, 5V rail•Theoretical threshold center is 2.5 V2.5 V2.5 V 2.5 V2.0 V2.0 V 4.8 V2.5 V2.51 V4.8 V 0.0 V0.0 V 5.0 VRissacher EE365Lect #10Metastability•Metastability is inherent in any bistable circuit•Two stable points, one metastable pointRissacher EE365Lect #10Another look at metastabilityRissacher EE365Lect #10“sube y baja” behaviorRissacher EE365Lect #10Why all the harping on metastability?•All real systems are subject to it–Problems are caused by “asynchronous inputs” that do not meet flip-flop setup and hold times.–Details in Chapter-7 flip-flop descriptions and in Section 8.9–Especially severe in high-speed systems– since clock periods are so short, “metastability resolution time” can be longer than one clock period.•Many digital designers, products, and companies have been burned by this phenomenom.Rissacher EE365Lect #10Back to the bistable….•How to control it?–Screwdriver–Control inputs•S-R latchRissacher EE365Lect #10S-R latch operationMetastability is possibleif S and R are negatedsimultaneously.(try it in Foundation)Rissacher EE365Lect #10S-R latch timing parameters•Propagation delay•Minimum pulse widthRissacher EE365Lect #10S-R latch symbolsRissacher EE365Lect #10S-R latch using NAND gatesRissacher EE365Lect #10S-R latch with enableRissacher EE365Lect #10D latchRissacher EE365Lect #10D-latch operationRissacher EE365Lect #10D-latch timing parameters•Propagation delay (from C or D)•Setup time (D before C edge)•Hold time (D after C edge)Rissacher EE365Lect #10Edge-triggered D flip-flop behaviorRissacher EE365Lect #10D flip-flop timing parameters•Propagation delay (from CLK)•Setup time (D before CLK)•Hold time (D after CLK)Rissacher EE365Lect #10TTL edge-triggered D circuit•Preset and clear inputs–like S-R latch•3 feedback loops–interesting analysis•Light loading on D and CRissacher EE365Lect #10CMOS edge-triggered D circuit•Two feedback loops (master and slave latches)•Uses transmission gates in feedback loops•Interesting analysis method (Sec. 7.9)Rissacher EE365Lect #10Other D flip-flop variations•Negative-edge triggered•Clock enable•ScanRissacher EE365Lect #10Scan flip-flops -- for testing•TE = 0 ==> normal operation•TE = 1 ==> test operation–All of the flip-flops are hooked together in a daisy chain from external test input TI.–Load up (“scan in”) a test pattern, do one normal operation, shift out (“scan out”) result on TO.Rissacher EE365Lect #10J-K flip-flops•Not used much anymoreRissacher EE365Lect #10T flip-flops•Important for countersRissacher EE365Lect #10In Class Practice ProblemThe characteristic Equation for a D latch is:Q* = DWrite the Characteristic Equation for an S-R latchRissacher EE365Lect #10In Class Practice ProblemThe characteristic Equation for an S-R latch is:Q* = S + R’ • QRissacher EE365Lect #10In Class Practice Problem #2Write characteristic equations for each of the following:•J-K flip flop•T flip flop•T flip flop with enableRissacher EE365Lect #10In Class Practice Problem #2Rissacher EE365Lect #10J-K flip flop:T flip flop:In Class Practice Problem #2Write characteristic equations for each of the following:•J-K flip flop–Q* = J • Q’ + K’ • Q•T flip flop–Q* = Q’•T flip flop with enable–Q* = EN • Q’ + EN’ • QRissacher EE365Lect #10•SSI LATCHES and Flip-FlopsRissacher EE365Lect #10Sequential PALs•16R8Rissacher EE365Lect #10One output of 16R8•8 product terms to D input of flip-flop–positive edge triggered, common clock for all•Q output is fed back into AND array–needed for state machines and other applications•Common 3-state enable for all output pinsRissacher EE365Lect #10PAL16R6•Six registered outputs•Two combinational outputs (like the 16L8’s)Rissacher EE365Lect #10GAL16V8•Each output is programmable as combinational or registered•Also has programmable output polarityRissacher EE365Lect #10GAL16V8 output logic macrocellRissacher EE365Lect #10GAL22V10•More inputs•More product terms•More flexibilityRissacher EE365Lect #10GAL22V10 output logic macrocellRissacher EE365Lect #10Next time•State

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