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CLARKSON EE 365 - LECTURE

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PowerPoint PresentationTopicsRole of MSI Components in Logic DesignMSI vs. Gate Level DesignSlide 5Programmable Logic Arrays (PLAs)Example: 4x3 PLA, 6 product termsCompact representationSome product termsPLA Electrical DesignProgrammable Array Logic (PALs)Slide 12Designing with PALsDecodersBinary 2-to-4 decoder2-to-4-decoder logic diagramMSI 2-to-4 decoderDecoder SymbolComplete 74x139 DecoderMore decoder symbolsMinterms & DecodersSlide 223-to-8 decoder74x138 3-to-8-decoder symbolDecoder cascadingIn-Class Practice ProblemSlide 27More cascadingDecoder applicationsNext timeEE365Adv. Digital Circuit DesignClarkson UniversityLecture #7Intro to MSIPLDs and DecodersTopics•MSI Intro•PLDs•DecodersRissacher EE365Lect #7Role of MSI Components in Logic Design•Gates are the fundamental building blocks of logic - the “atoms”.•Medium Scale Integrated (MSI) components are the “molecules” - the commonly occurring functions.•MSI components form the building blocks for much more complex functions .Rissacher EE365Lect #7MSI vs. Gate Level Design•Functions more complex - more inputs and/or outputs.•Find a good, feasible design, not necessarily optimal.•Not restricted to two-level logic.•Trade-off propagation delay with simplicity of design.•Keep IC count low (usually ignore gate count).Rissacher EE365Lect #7MSI vs. Gate Level Design•Look for designs which are scalable - easily expanded to handle more inputs.•Look for designs which are hierarchical - built upon already designed functions.•No automated, general design algorithm - must be creative.•Same principles apply to custom VLSI or ASIC design.Rissacher EE365Lect #7Programmable Logic Arrays (PLAs)•Any combinational logic function can be realized as a sum of products.•Idea: Build a large AND-OR array with lots of inputs and product terms, and programmable connections.–n inputs•AND gates have 2n inputs -- true and complement of each variable.–m outputs, driven by large OR gates•Each AND gate is programmably connected to each output’s OR gate.–p AND gates (p<<2n)Rissacher EE365Lect #7Example: 4x3 PLA, 6 product termsRissacher EE365Lect #7Compact representation•Actually, closer to physical layout (“wired logic”).Rissacher EE365Lect #7Some product termsRissacher EE365Lect #7PLA Electrical Design•See Section 5.3.5 -- wired-AND logicRissacher EE365Lect #7Programmable Array Logic (PALs)•How beneficial is product sharing?–Not enough to justify the extra AND array•PALs ==> fixed OR array–Each AND gate is permanently connected to a certain OR gate.•Example: PAL16L8Rissacher EE365Lect #7•10 primary inputs•8 outputs, with 7 ANDs per output•1 AND for 3-state enable•6 outputs available as inputs–more inputs, at expense of outputs–two-pass logic, helper terms•Note inversion on outputs–output is complement of sum-of-products–newer PALs have selectable inversionRissacher EE365Lect #7Designing with PALs•Compare number of inputs and outputs of the problem with available resources in the PAL.•Write equations for each output using ABEL.•Compile the ABEL program, determine whether minimimized equations fit in the available AND terms.•If no fit, try modifying equations or providing “helper” terms.Rissacher EE365Lect #7Decoders•General decoder structure•Typically n inputs, 2n outputs–2-to-4, 3-to-8, 4-to-16, etc.Rissacher EE365Lect #7Binary 2-to-4 decoderNote “x” (don’t care) notation.Rissacher EE365Lect #72-to-4-decoder logic diagramRissacher EE365Lect #7MSI 2-to-4 decoder•Input buffering (less load)•NAND gates (faster)Rissacher EE365Lect #7Decoder SymbolRissacher EE365Lect #7Complete 74x139 DecoderRissacher EE365Lect #7More decoder symbolsRissacher EE365Lect #7Minterms & DecodersRissacher EE365Lect #7Note that outputs to decoders correspond to MintermsMinterms & DecodersRissacher EE365Lect #7• SOP can be formed by combining outputs• i.e., Z = (I0’ • I1’) + (I0 • I1’)• Most Decoders have active-low outputs, so they need to be inverted or a NAND can be substituted3-to-8 decoderRissacher EE365Lect #774x138 3-to-8-decoder symbolRissacher EE365Lect #7Decoder cascading4-to-16 decoderRissacher EE365Lect #7In-Class Practice Problem•Wire the 74x139 to make a 3-to-8 decoder•You may use invertersRissacher EE365Lect #7In-Class Practice Problem•Note that this would not normally be done since the 74x138 does the same thingABCRissacher EE365Lect #7More cascading5-to-32 decoderRissacher EE365Lect #7Decoder applications•Microprocessor memory systems–selecting different banks of memory•Microprocessor input/output systems–selecting different devices•Microprocessor instruction decoding–enabling different functional units•Memory chips–enabling different rows of memory depending on address•Lots of other applicationsRissacher EE365Lect #7Next time•Buffers•Drivers•Encoders•Multiplexers•Exclusive OR GatesRissacher EE365Lect


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CLARKSON EE 365 - LECTURE

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