ColorGrayscaleEE 200 Spring 2014Lab 4.EE 200Design ToolsLaboratory 4Professor Jeffrey SchianoDepartment of Electrical Engineering1EE 200 Spring 2014Lab 4.Laboratory 4 Topics• Finite state machine realization using Karnaugh maps and discrete-logic• Discrete-logic simulation using Multisim• EE 210 review: phasors and filters• LabVIEW front panel and block diagram– Toolbars– Terminology2EE 200 Spring 2014Lab 4.Parity Detector• Parity bits are extra signals added to a data word to enable error checking• There are two types of Parity – even and odd• A string of bits has even (odd) parity if the number of 1’s in the string is even (odd)3EE 200 Spring 2014Lab 4.Parity Detector Project• Realize the parity detector using – Discrete logic– Programmable logic device– Embedded microcontroller– Data acquisition device (DAQ)• Compare the four implementations – The number of integrated circuits– The power consumption of the design– The ability to modify the design– The implementation cost • Repeat the process for the autonomous robot (Lecture 3)4EE 200 Spring 2014Lab 4.Exercise 1• Design a Moore finite state machine that accepts a bit stream and outputs a 0 if the parity thus far is even and a 1 if the parity is odd• Realize the parity detector using only NAND gates and D-type flip-flops5INPUTOUTPUTCLOCKEE 200 Spring 2014Lab 4.Exercise 1: State Diagram6EE 200 Spring 2014Lab 4.Exercise 1: State Table7EE 200 Spring 2014Lab 4.Exercise 1: Excitation and Output Equations8EE 200 Spring 2014Lab 4.Exercise 1: Realization using NAND Gates and D-Type Flip-Flops9EE 200 Spring 2014Lab 4.Exercise 2• Use Multisim to simulate the parity detector in Exercise 1 • Realize the circuit using discrete-logic – CD4011BD Quad 2-Input NAND Gate– CD4013BD Dual D-Type Flip-Flop• Generate the input x using an interactive switch that toggles when x is depressed on the key board; indicate the state of the input using a blue LED• Generate a 0.5 Hz clock signal using the Agilent Fcn Gen• View the input, output, and clock using the four channel scope, assign different trace colors to the three signals• Set the simulation End time (TSTOP) to 1000 s10EE 200 Spring 2014Lab 4.Exercise 2: Schematic Capture11EE 200 Spring 2014Lab 4.Exercise 2: Function Generator12• Select the square-wave output• Set the frequency to 500 mHz• Set the output amplitude to 5 Vpp• Set the offset to 2.5 VEE 200 Spring 2014Lab 4.Exercise 2: Trace Color13• Right click wire, and select Segment Color– Use Blue for the input x on scope channel B– Use Green for the output y on scope channel CEE 200 Spring 2014Lab 4.Exercise 2: Simulation End Time• Set simulation End time (TSTOP) to 1000 s– Simulate >> Interactive Simulation Settings >>Defaults for transient analysis instruments14EE 200 Spring 2014Lab 4.Exercise 2: Simulation Results15yxclockEE 200 Spring 2014Lab 4.Phasors and Low-pass Filters• Analog to Digital Conversion  ADC  A/D  A2D– Transforms an analog signal to a digital signal• Low-pass filters proceed ADCs to avoid aliasing, aphenomenon where the sampling process causes high frequency analog signals to appear as low frequency digital signals• Later this semester we will consider ADCs and aliasing in greater depth16EE 200 Spring 2014Lab 4.Key Concepts• Characteristics of the sinusoidal response of linear systems– The frequency of the response is the same as the frequency of the source– The amplitude of the response is equal to the amplitude of the source multiplied by the magnitude of the frequency response function– The phase angle of the response is equal to the phase angle of the source plus the phase angle of the frequency response function17EE 200 Spring 2014Lab 4.Frequency Response FunctionLinearNetwork()invt ()outvt18Time Domain: () cosPhasor Domain: iin i ijin ivt A tVAeTime Domain: () cosPhasor Domain: oout o ojout ovt A tVAe()polar representation Frequency Response Function () ()jHjoutinVHj Hj eV• Tool for determining the sinusoidal steady-state responseEE 200 Spring 2014Lab 4.Sinusoidal-Steady Response19() Rejtout outvt Ve() ( ) cos ( )    ooout i iAv t Hj A t Hj() ( ) Re ( ) Re ( )iVout ooutout ojt Hjjtout in iVVAvt HjVe Hj Ae        EE 200 Spring 2014Lab 4.Exercise 3• Consider an RC circuit with input f(t) and output y(t)• Determine the polar form of the frequency response function• For c= 1/RC, find the steady-state response y(t) forf(t) = cos(0.1 ct) + cos(1.0 ct) + cos(10 ct)20RC()yt()ftEE 200 Spring 2014Lab 4.Exercise 321EE 200 Spring 2014Lab 4.Exercise 322EE 200 Spring 2014Lab 4.Exercise 323EE 200 Spring 2014Lab 4.Exercise 324EE 200 Spring 2014Lab 4.LabVIEW: Review• Open math(SubVI).vi• LABVIEW VIs contain three main components:1. Front Panel 3. Icon/Connector Pane2. Block Diagram25EE 200 Spring 2014Lab 4.Front Panel – Controls Palette• Contains the controls and indicators you use to create the front panel• Access by– select View >> Controls Palette, or– right-click on front panel26EE 200 Spring 2014Lab 4.Front Panel Toolbar27RunRun ContinuouslyAbort ExecutionPauseText SettingsAlign ObjectsDistribute ObjectsResize ObjectsReorder ObjectsEE 200 Spring 2014Lab 4.Front Panel – Controls & Indicators• Controls– Knobs, push buttons, dials, and other input devices– Simulate instrument input devices and supply data to the block diagram of the VI• Indicators– Graphs, LEDs, and other displays– Simulate instrument output devices and display data the block diagram acquires or generates28EE 200 Spring 2014Lab 4.Front Panel –Numeric Controls/Indicators• The numeric data type can represent numbers of various types, such as integer or real29NumericControlsNumericIndicatorsIncrement/DecrementEE 200 Spring 2014Lab 4.Front Panel –Boolean Controls/Indicators• The Boolean data type represents data that only has two parts, such as True and False or On and Off• Use Boolean controls and indicators to enter and display Boolean (True or False) values•