ColorGrayscaleEE 200 Fall 2014Lab 2.EE 200Design ToolsLaboratory 2Professor Jeffrey SchianoDepartment of Electrical Engineering1EE 200 Fall 2014Lab 2.Laboratory 2 Topics• Review Material– EE 210 and CMPEN 270• LabVIEW–Review– Coercion Dots and Numeric Conversion– Function Nodes2EE 200 Fall 2014Lab 2.Exercise 1• Sketch the typical input-output transfer characteristic, VOUTversus VIN, of the CMOS inverter• Indicate on the diagram – VOHmin: minimum output voltage in the HIGH state– VIHmin: minimum input recognized as a HIGH – VILmax: maximum input recognized as a LOW– VOLmax: maximum output voltage in the LOW stateOUTVINVDDVSSV3EE 200 Fall 2014Lab 2.Exercise 1HighStateLowState4OUTVINVDDVDDV2DDV2DDVEE 200 Fall 2014Lab 2.Exercise 2• The ring oscillator generates the waveforms shown• Determine the values of vA, vB,and vC, in terms of VDD• Find expressions for TL, TH, and in terms of R and CCoutvRsRfvCMOS CMOS0LV HDDVVHTLToutvtBvAvtCvfv1LHfTT5EE 200 Fall 2014Lab 2.Exercise 2• Suppose gate B output is logic high• Gate A input must be logic high which means vf> VDD/2• Because gate A output is logic low, vfrelaxes towards 0• When vfreaches VDD/2, gate A and B outputs switch state• Because voltage across C cannot change instantaneously, the instant gate A switches, vfmust decrease by VDD6CoutvRsR2fDDvVABHVLVfv0LV HDDVVoutvttfvBv0.5DDV0.5DDVCvDDVEE 200 Fall 2014Lab 2.Exercise 2• Suppose gate B output is logic low• Gate A input must be logic low which means vf< VDD/2• Because gate A output is high, vfheads towards VDD• When vfreaches VDD/2, gate A and B outputs switch state• Because voltage across C cannot change instantaneously, the instant gate A switches, vfmust increase by VDD7CoutvRsR2fDDvVABLVHVfv0LV HDDVVoutvttfv0.5BDDvVDDV1.5ADDvVDDVEE 200 Fall 2014Lab 2.Exercise 2• The behavior of vf(t) is determined by the RC circuit• From Laboratory 1, during the intervals THand TL8() ,initial voltagefinal voltage  tfFIFIFvt V V Ve RCVVLVHVHTLToutvt0.5DDV1.5DDVt0.5DDVfvEE 200 Fall 2014Lab 2.Exercise 29EE 200 Fall 2014Lab 2.Exercise 210EE 200 Fall 2014Lab 2.Circuit Simulation• EE 210 – Provides an Introduction to NI Multisim– Multisim is a SPICE Simulation Environment• Simulation Program with Integrated Circuit Emphasis• EE 200 – Mixed-Signal Circuits (analog and digital)– SPICE Models– Custom components– Export to printed circuit board layout tool (NI Ultiboard)11EE 200 Fall 2014Lab 2.Mixed-Signal Circuit Simulation• Circuits containing both analog and digital signals are referred to as mixed-signal circuits• Owing to the nonlinear dynamic behavior of devices, simulation of mixed-signal circuits requires knowledge of both the device models and numerical integration methods; both beyond the scope of EE 200• Exercise 3 demonstrates that simulation tools such as Multisim yield an incorrect results when used improperly12EE 200 Fall 2014Lab 2.Exercise 3• Consider the ring oscillator with VDD= 5V• Choose Rs= 120 k, R = 56 k, C = 0.22 µF13CoutvRsRfvCMOS CMOS0V5VHTLToutvt2.5V7.5Vt2.5Vfv1137Hz, T 27ms2ln(3)fRC fEE 200 Fall 2014Lab 2.Exercise 3 – Schematic Capture• Realize using a CD4011BD Quad 2-Input NAND Gate and observe waveforms using the Agilent oscilloscope14EE 200 Fall 2014Lab 2.Simulation with Default Settings15• What is wrong?– Shape of the waveform for vf (blue curve, channel 2)– Amplitude of the waveform for vfEE 200 Fall 2014Lab 2.Modification – Initial Conditions• Set initial output state of U1A (low, 0V) and U1B (high, 5V)16EE 200 Fall 2014Lab 2.Modification – Analysis Options• Simulate >> Interactive simulation settings17EE 200 Fall 2014Lab 2.Modification – Analysis Options• Simulate >> Interactive simulation settings• Select Use custom settings on Analysis options tab• Set number of iterations and integration method as shown18EE 200 Fall 2014Lab 2.Simulation with Custom Settings19• Agrees with theoretical analysis:– Shape of the waveform for vf (blue curve, channel 2)– Amplitude of the waveform for vfEE 200 Fall 2014Lab 2.Exercise 4• Which node(s) executes first: Add or Subtract?• Which node(s) executes last?20EE 200 Fall 2014Lab 2.Exercise 5• Which node(s) may execute first?21EE 200 Fall 2014Lab 2.Coercion Dots• Typically, when you wire different representation types to the inputs of a function, the function returns an output in the larger or wider format• LabVIEW chooses the representation that uses more bits22coercion dotEE 200 Fall 2014Lab 2.Numeric Conversion• Avoid coercion for better performance– Choose matching data type– Programmatically convert to the matching data type23EE 200 Fall 2014Lab 2.Conversion Palette24EE 200 Fall 2014Lab 2.Exercise 6• Write a VI that determines the roots of the quadratic equation with real-valued parameters a, b, c• Display the roots using a double complex indicator• Implement using function nodes• Eliminate coercion dots2520ax bx cEE 200 Fall 2014Lab 2.Exercise 626EE 200 Fall 2014Lab 2.Exercise 7• Repeat Exercise 6 using a Formula Node• Do Formula Nodes support complex valued variables?– Review the Formula Node Syntax page27EE 200 Fall 2014Lab 2.Exercise 728EE 200 Fall 2014Lab 2.Complex Palette29EE 200 Fall 2014Lab 2.EE 200Design ToolsLaboratory 2Professor Jeffrey SchianoDepartment of Electrical Engineering1EE 200 Fall 2014Lab 2.Laboratory 2 Topics• Review Material– EE 210 and CMPEN 270• LabVIEW–Review– Coercion Dots and Numeric Conversion– Function Nodes2EE 200 Fall 2014Lab 2.Exercise 1• Sketch the typical input-output transfer characteristic, VOUTversus VIN, of the CMOS inverter• Indicate on the diagram – VOHmin: minimum output voltage in the HIGH state– VIHmin: minimum input recognized as a HIGH – VILmax: maximum input recognized as a LOW– VOLmax: maximum output voltage in the LOW state3EE 200 Fall 2014Lab 2.Exercise 14EE 200 Fall 2014Lab 2.Exercise 2• The ring oscillator generates the waveforms shown• Determine the values of vA, vB,and vC, in terms of VDD• Find expressions for TL, TH, and in terms of R and C5EE 200 Fall 2014Lab 2.Exercise 2• Suppose gate B output is logic high• Gate A input must be logic high which means vf> VDD/2• Because gate A output is logic low, vfrelaxes towards 0• When vfreaches VDD/2, gate A and B outputs switch state• Because