EGR426 W’10Learning Activity #5Objectives• Practice using the Xilinx CORE Generator (CoreGen) to create pre- defined components• Practice integrating pre-defined components into a user applicationPart I – A Restricted Counter1. Use the Xilinx CORE Generator (Start Menu->Xilinx 10.1i->ISE->Ac cessories->CORE Generator)to create a 4-bit counter that counts between 1 and 9.(a) Select File->New Project.(b) Call the new project ’counter4bit.cgp’ and modify the output directory as desired. Make a noteof the director y that you choose!(c) In the next dialog, set the proper part family (Spartan-3E), device (xc3s500e or xc3s1200e),package (fg320), and speed grade (-5).(d) Click on the “Generation” tab at the top of the dialog and make sure that the Design Entrydrop-down box is set to VHDL, and the Vendor (under Flow Settings) is set to ISE. Click OK.(e) From the tree control on the left side of the main CoreGen window, open the Basic Elements tree,then the Counters tree.(f) Select the “Binary Counter” item.(g) On the right-side window, click on the “Customize” link.(h) A parameterization dialog opens for the counter. On the first pa ge of the dialog, make sure youset:i. T he Output Width to 4ii. The Step Value to 1iii. The restrict count to checkbox should be checkediv. The Final Count value to 9You can leave the default settings on pa ges 2 and 3 of the dialog.(i) Click the Finish button to generate the counter.2. Cre ate a new project in Xilinx ISE. In the New Project Wizard, use the CoreGen-generated .XCO fileas an existing source file for the project.Note that this project cannot be synthesized. To actually use the counter in your design, you will haveto instantiate your component (using the VHDL structural paradigm). The CoreGen-generated .VHOfile shows you how to both declare the component and instantiate it.3. Add a new VHDL source file to your design. This will be the top-level file and will instantiate yourcore. Its entity declaration should be the same as that of your counter:ENTITY counter4PORT(CLK : IN STD_LOGIC;Q : OUT STD_LOGIC_VECTOR(3 downto 0));END ENTITY;4. Use the .VHO file generated by CoreGen as a guide for how to instantiate the counter:1(a) The COMPONENT declaration goes between ARCHITECTURE and BEGIN(b) The instantiation of your component goes after the BEGIN5. Synthesize your design.6. Switch to Behavioral Simulation and create a graphical testbench waveform tha t lasts for 3000 ns. Usethe default clock values (100ns high/low time, 15ns setup/h old time, 100ns reset signal).7. Simulate your design and ma ke sure it behaves as expected.NOTES1. Think about how you implemented your design. You now have a “black box” in your design that isnon-portable and specific to the Xilinx architecture and toolchain.Yes, CoreGen is a timesaver and there are some powerful building blocks available, but by using theseblocks you are “drinking the Xilinx Kool-Aid” and will have very non-portable code. If you ever switchto Altera devices, any CoreGen-generated blocks must be recreated, and any of your own VHDL codethat interfaces with these block s must be rewritten, retested, etc. Writing your own behavioral VHDLcode means your code will be portable to any VHDL-based flow from any vendor.2. This is not entirely true, as Xilinx provides the VHDL source code for their pr e defined blocks (see,for ex ample C:\Xilinx\10.1\ISE\vhdl\src\XilinxCoreLib\c_counter_binary_v10_0.vhd). How-ever, this code instantiates (structurally ) other Xilinx blocks, and you never know when you’re going torun into a “binary blob” or something like