EGR426 W’10Learning Activity #3Objectives• Become familiar with representing and manipulating buses in VHDL• Become familiar with bus simulations in the Xilinx ISE Simulator• Become familiar with the numeric interpretation of buses in VHDLPart I – The STD_LOGIC_VECTOR Type1. Create a new project named ’slvtest’ with a 10 -bit bus input a nd one output.2. Following Figure 1 on page 40 o f your lecture notes, implement a 10-bit NAND gate (just a littledifferent from the 10-bit AND gate shown in the figure ... you’ll proba bly use the VHDL ’no t’ operator).3. Add a new Te stbench Waveform source to your project called ’slvtest_test’. In the Initial Timingand Clock Wizard, set the Combinatorial Timing Information values to 10ns for Check Outputs and10ns for Assign Inputs.Set the length of the test bench to210· 20ns + 100ns≈ 21000ns.4. With a bus input of type STD_LOGIC_VECTOR, the graphical simulator displays your input signalas a proper bus. To test all possible input values, click on the input waveform just past the 100nsmark (you’ll have to zoom in first), then select Set Value. Click on the Pattern Wizard button. In thePattern Type drop-down list select Count Up. Then set the Number of Cycles to 210= 1024. Click onthe Decimal radix button, then ensure that the remaining fields at the bottom of the dialog are set upto count up by 1 every clock: Initial Value is 0, Increment By is 1, Terminal Value is 1023, and CountEvery is 1.In the Processes window, you will have to right-click on Simulate Behavioral Model, select Properties,and set the Simulation Run Time to 2100 0ns.Ensure that your design works properly. You may have to zoom in to see the details of each count.Also, right-click on the inx[9:0] bus name in the simulation results and s e t the radix to “Decimal(Unsigned)” to see count numbers in decimal.5. Go back to the Implementation w indow and double-click on the Implement Design item in the Processe swindow. Then, open the Design Summar y window tab and click on the Sta tic Timing Report link (inthe Detailed Reports sec tion at the bottom).Compare the worst-case propagation delay of this 10-input NAND gate to the 3-input AND gate fromthe previous learning activity (which should have been somewhere around 5 ns).How does this cor relate with your understanding of the underlying Spartan3E architecture? How manyinputs does an L UT have? How many LUT’s are necessa ry for implementing a 10-bit NAND gate?6. Open the Implement Design tree control, then the Place & Route tree control, then double-click onthe Generate Post-Place & Route Simulation Model item. Use the File–>Open menu to navigate tothe directory that your project files are in, then find the netgen subdirecto ry, and within that the parsubdirectory. In that subdirectory, open up the file slvtest_timesim.vhd (this is the post-place &route simulation model that was generated).Note that this is a VHDL file written in the “structural” style. It lists “primitive” components that mapdirectly to XC3S500E resources (e.g., LUT’s as component name X_LUT4, I/O buffers as componentname X_BUF and X_OBUF, etc.) These primitive components were declared in the SIMPRIM libraryincluded at the top of the file.1Look for components of type X_LUT4. How many of them are there? See if you can follow thestructural style and draw a schematic of what goes in to each LUT and what comes out.7. Back in the Processes window, open up the Synthesize-XST tree control and double-click on the ViewRT L Schematic item. A new Design tab appears at the bottom of the Sources window. Click on it,open up the slvtest tree c ontrol and double-click on the item within. Doe s this schematic correspondto the post-pla c e & route simulation model?Remember that the “Synthesis” phase of the flow translates your VHDL code to a generic representationof the ha rdware that would implement your model. The subsequent steps of transla tion, map, a ndplace&route take this generic representation and fit it onto the actual hardware resources (e.g., 4-inputLUT’s) available o n the device you have chosen.8. Directly below the View RTL Schematic item you will see a View Technology Schematic item. Double-click on that, then click on slvtest in the Design tab of the Sources window. Now how does thisschematic c orrespond to the VHDL post-place & route simulation model?Part II – The UNSIGNED Type1. Create a new project named ’addone’, with ’addone.vhd’ as the top-level VHDL file. The goal ofthis circuit is to accept a 4-bit bus DATA and to output another 4-bit bus DATAOUT that is the valueof the DATA bus plus one, using the unsigned interpretation of the 4-bit bus.Make sure you leave the ENTITY decla ration of the DATA and DATAOUT buses to be of typeSTD_LOGIC_VECTOR!2. Use the simulator to verify that your circuit