VHDL GlossaryExamplescomp.lang.vhdlFrequently Asked Questions And Answers (Part 4):VHDL GlossaryPreliminary RemarksThis part of the FAQ is reprinted from IEEE Std 1076-1993 IEEE Standard VHDL LanguageReference Manual, Copyright © 1994 by the Institute of Electrical and Electronics Engineers,Inc. The IEEE disclaims any responsibility or liability resulting from the placement and use inthis product. Information is reprinted with the permission of the IEEE. Further distribution is notpermitted without consent of the IEEE Standards Department. This is a monthly posting to comp.lang.vhdl containing a VHDL glossary. Please send additionalinformation directly to the editor: [email protected] (Edwin Naroska)Corrections and suggestions are appreciated. Thanks for all corrections. There are three other regular postings: part 1 lists general information on VHDL, part 2 listsbooks on VHDL, part 3 lists products and services (PD+commercial). The following text is reprinted from the Annex B of the IEEE Std 1076-1993 IEEE StandardVHDL Language Reference Manual. Text added by the editor of the FAQ is enclosed in squarebrackets . Note, the html links and the examples are not part of the original IEEE document.VHDL GlossaryThis glossary contains brief, informal descriptions for a number of terms and phrases used todefine this language. The complete, formal definition of each term or phrase is provided in themain body of the standard.For each entry, the relevant clause numbers [(of the VHDL Language Reference Manual)] in thetext are given. Some descriptions refer to multiple clauses in which the single concept isdiscussed; for these, the clause number containing the definition of the concept is given in italics.Other descriptions contain multiple clause numbers when they refer to multiple concepts; forthese, none of the clause numbers are italicized.B.1 abstract literal: A literal of the universal_real abstract type or the universal_integer abstract type. (§13.2, §13.4)B.2 access type: A type that provides access to an object of a given type. Access to such an object is achieved by an access value returned by an allocator; the access value is said to designate the object. (§3, §13.3)[Example E.1] B.3 access mode: The mode in which a file object is opened, which can be either read-only orwrite-only. The access mode depends on the value supplied to the Open_Kind parameter. (§3.4.1, §14.3).B.4 access value: A value of an access type. This value is returned by an allocator and designatesan object (which must be a variable) of a given type. A null access value designates no object. Anaccess value can only designate an object created by an allocator; it cannot designate an objectdeclared by an object declaration. (§3, 3.3)[Example E.1] B.5 active driver: A driver that acquires a new value during a simulation cycle regardless ofwhether the new value is different from the previous value. (§12.6.2, §12.6.4)B.6 actual: An expression, a port, a signal, or a variable associated with a formal port, formal parameter, or formal generic. (§1.1.1.1, §1.1.1.2, §3.2.1.1, §4.3.1.2, §4.3.2.2, §5.2.1, §5.2.1.2)B.7 aggregate:1. The kind of expression, denoting a value of a composite type. The value is specified bygiving the value of each of the elements of the composite type. Either a positional association or a named association may be used to indicate which value is associated withwhich element. - 1 -VHDL GlossaryFAQ comp.lang.vhdl part 4 (VHDL Glossary)2. A kind of target of a variable assignment statement or signal assignment statement assigninga composite value. The target is then said to be in the form of an aggregate. (§7.3.1, §7.3.2,§7.3.4, 7.3.5, §7.5.2) [Example E.2] B.8 alias: An alternate name for a named entity. (§4.3.3)B.9 allocator: An operation used to create anonymous, variable objects accessible by means of access values. (§3.3, §7.3.6)B.10 analysis: The syntactic and semantic analysis of source code in a VHDL design file and theinsertion of intermediate form representations of design units into a design library. (§1 1.1, §11.2, §11.4)B.11 anonymous: The undefined simple name of an item, which is created implicitly. The base type of a numeric type or an array type is anonymous; similarly, the object denoted by an access value is anonymous. (§4.1)B.12 appropriate: A prefix is said to be appropriate for a type if the type of the prefix is the typeconsidered, or if the type of the prefix is an access type whose designated type is the typeconsidered. (§6.1)B.13 architecture body: A body associated with an entity declaration to describe the internalorganization or operation of a design entity. An architecture body is used to describe thebehavior, data flow, or structure of a design entity. (§1, §1.2)B.14 array object: An object of an array type. (§3)[Example E.3] B.15 array type: A type, the value of which consists of elements that are all of the same subtype(and hence, of the same type). Each element is uniquely distinguished by an index (for aone-dimensional array) or by a sequence of indexes (for a multidimensional array). Each indexmust be a value of a discrete type and must lie in the correct index range. (§3.2.1)[Example E.3] B.16 ascending range: A range L to R. (§3.1)B.17 ASCII: The American Standard Code for Information Interchange. The package Standardcontains the definition of the type Character, the first 128 values of which represent the ASCIIcharacter set. (§3.1.1, §14.2)- 2 -VHDL GlossaryB.18 assertion violation: A violation that occurs when the condition of an assertion statementevaluates to false. (§8.2)[Example E.4] B.19 associated driver: The single driver for a signal in the (explicit or equivalent) processstatement containing the signal assignment statement. (§12.6.1)B.20 associated in whole: When a single association element of a composite formal supplies theassociation for the entire formal. (§4.3.2.2)B.21 associated individually: A property of a formal port, generic, or parameter of a composite type with respect to some association list. A composite formal whose association is defined bymultiple association elements in a single association list is said to be associated individually inthat list. The formats of such association elements must denote non-overlapping subelements or slices of the formal. (§4.3.2.2)B.22 association element: An element that associates an actual or local with a local or formal. (§4.3.2.2)B.23