EGR426 W’10Learning Activity #2Objective• To practice using behavioral and post-route test benches in VHDLPart I – Behavioral Simulation1. Create a new Xilinx ISE project with VHDL as the top-level source file. Call the project ’anotherand3’and name the top-level file anotherand3.vhd. To refresh your memory, in the New Project Wizard:• Make sure the Top-Level Source Type is HDL, same Spartan 3E device as before, etc.• In the Create New Source dialog, press the New Source button to cre ate a top-level VHDL file, asyou did before. Specify a “VHDL Module” with name anotherand3.vhd.• In the Define Module dialo g, add 3 input ports named IN1 through IN3 and one output p ortnamed OUTX.• Keep clicking Next and finally Finish.2. Once the project is created, edit the anotherand3.vhd file. You need to fill in the details of the3-input AND gate implementation between the “begin” and “end Behavioral;” lines. Let’s do this onein yet another way:• Position the cursor on the line below “begin”.• From the Edit menu, select “L anguage Templates...”.• Open up the VHDL tree control, then the Synthesis Constructs tree control, then the Conditionaltree contro l. Finally, selec t (highlight) the Select/When Statement, and r ight-click to select “usein file”.• Return to your anotherand3.vhd file and “fill in the blanks” as fo llows:with inputs selectOUTX <= ’1’ when "111",’0’ when others;• The sig nal ’inputs’ must be defined between the “architecture” and “begin” lines as follows:SIGNAL inputs : STD_LOGIC_VECTOR(2 downto 0);• Finally, the signal ’inputs’ must be assigned to as follows, direc tly above the ’with’ line:inputs <= IN1 & IN2 & IN3;3. Synthesize your project by clicking on the Processes window, Processes tab, and double-clicking onSynthesize-XST.4. Switch the Sources window’s drop-down list box to “B e havioral Simulation”. Right-click on the anoth-erand3 file name and selec t “ New Source...”. For the type of file, select “VHDL Test bench”. Set thefile name to anotherand3_test.5. Once the source file is created, follow Figure 4 on pa ge 34 of your lecture notes to write the main partof the test bench. Note that much of the skeleton has already been created for you. Write the first testcase then use cut-and-paste libe rally.6. Open up the Xilinx ISE Simulator tree control and double-click on Simulate Be haviora l Model. Thereshould be no assertion errors.1Part II – Timing SimulationIn Part I you performed a simulation using a behavioral model only, as diagrammed in Figure 2 on page32 of your lecture notes. Now, we will “place and route” the design onto actual hardware and construct afull-timing simulation, as diagrammed in Fig ure 3 on page 33.1. Switch the Sources window drop-down list box to “Post-Route Simulation”. In the Process window,open the Xilinx ISE Simulator tree control and double-click on “Simulate Post-Place & Route Model”.Doing so automatically runs the “Implement Design” proce sses that you would normally execute in the“Synthesis/Implementation” view from the Sources window. You can go back there now and verifythat there are green checkmarks next to the Tr anslate, Map, and Place&Route items in the ImplementDesign tree control. Switch back to the Post-Route Simulation window view.2. Note that simulation failed. The Simulation window also shows tha t the OUTX signal never goes high.Why? Look back at your VHDL code – if you typed in the code from page 34 of your lectur e notesverbatim, then your code is only waiting 1ns from the time that stimulus is applied to the time thatthe output OUTX is checked. The actual FPGA has a larger propagation delay than this, so the fulltiming simulation using actual device timings fails.3. Modify your VHDL code to wait 10ns to check OUTX after applying stimulus, then re-run the Post-Route Simulation. Now it should work.4. Click on the Design Summary tab at the bottom o f the main editor window. Scroll down to seethe Detailed Reports section, then click on the Static Timing Report link. You should see that thepropagation delay of your 3-input-AND gate is on the order of 5ns, so 1ns is definitely too sho rt a timeto wait for inputs to propagate to outputs, and 1 0ns is definitely long enough.Notes1. The “Select/When” construct of VHDL is just a compact way of writing IF-THEN-ELSE statements. Itworks particularly well for decoders, such as the LED decoder some of you have to write. For example:with inputs selectled_outputs <= "1011001" when "000","1000110" when "001","0110001" when "010",-- etc. etc."1111111" when others;Of course, the value to assign to “led_outputs” depends upon which LED segments you want lit. Thevalues shown in the example above are just random numbers.2. In L ab #1 you’ve seen that you can generate “self-checking test benches”, in which the whole test bench(including stimulus and verification) is generated by Xilinx ISE! This seems to be a big time saver butit’s only half-true. It does save time in that this process creates a test bench skeleton complete withdetailed text reports, etc. Feel free to use that. It is NOT use ful, however, to just use the generatedtest bench, since the test bench verification was inferred by looking at the output of the VHDL entitythat you created; that is, it already assumed your hardware was correct. Think about it this way: ifyou were a teacher, would you use a student’s exam as the answer key for his /her exam?YOU have to write the stimulus and verification based upon your EXPECTED operation of the VHDLentity. If the ACTUAL and EXPECTED behavior differ, then you’ve found a bug. In fact, it is not abad idea to wr ite the test bench first (the principle behind “Test-Driven Development” in the softwareworld) so that you don’t fool yourself into writing test bench code that just mimics what the VHDLentity is doing (rather than what it’s SUPPOSED to be